PSB3186FV1.4XT Infineon Technologies, PSB3186FV1.4XT Datasheet - Page 161

• Manufacturer Part Number: PSB3186FV1.4XT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MCDA
MOR
DIOM_SDS ... DU/DD on IOM Controlled via SDS
0: The pin SDS and its configuration settings are used for serial data strobe only. The
IOM-2 data lines are not affected.
1: The DU/DD lines are deactivated during the during High/Low phase (selected via
DIOM_INV) of the SDS signal. The SDS timeslot is selected in SDS_CR.
SDS_BCL ... Enable IOM Bit Clock for SDS
0: The serial data strobe is generated in the programmed timeslot.
1: The IOM bit clock is generated in the programmed timeslot.
4.3.13
Value after reset: FF
MCDAxy ... Monitoring CDAxy Bits
Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register.
This can be used for monitoring the D-channel bits on DU and DD and the ’Echo bits’ on
the TIC bus with the same register
4.3.14
Value after reset: FF
Contains the MONITOR data received in the IOM-2 MONITOR channel according to the
MONITOR channel protocol. The MONITOR channel (0-7) can be selected by setting the
monitor channel select bit MON_CR.MCS.
Data Sheet
7
7
MCDA - Monitoring CDA Bits
MOR - MONITOR Receive Channel
Bit7
MCDA21
Bit6
H
H
Bit7
MCDA20
Monitor Receiver Data
Bit6
161
Bit7
MCDA11
Bit6
Detailed Register Description
Bit7
MCDA10
0
0
Bit6
ISAC-SX TE
PSB 3186
2003-01-30
RD (5C)
RD (5B)