PSB3186FV1.4XT Infineon Technologies, PSB3186FV1.4XT Datasheet - Page 102

• Manufacturer Part Number: PSB3186FV1.4XT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.8
The ISAC-SX TE contains an HDLC controller for the layer-2 functions of the D- channel
protocol (LAPD). By setting the Enable HDLC channel bits (D_EN_x) in the DCI_CR
register the HDLC controller can access the D or B-channels on IOM-2.
It performs the framing functions used in HDLC based communication: flag generation/
recognition, bit stuffing, CRC check and address recognition.
The FIFO has a size of 64 byte per direction and is implemented as cyclic buffers. The
transceiver reads and writes data sequentially with constant data rate whereas the data
transfer between FIFO and microcontroller uses a block oriented protocol with variable
block sizes.
The configuration, control and status bits related to the HDLC controller are all assigned
to the following address ranges:
Table 14
D-channel HDLC
Note: For D-channel access the address range 00
3.8.1
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a D-channel two-byte address (LAPD) is shown below:
For address recognition on the D-channel the ISAC-SX TE contains four programmable
registers for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values
for the “group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which must be set to ’1’ according to HDLC LAPD.
Data Sheet
SAPI1, 2, SAPG
TE PSB 2186), however a single address from this range is sufficient to access
the FIFO as the internal FIFO pointer is incremented automatically independent
from the external address.
High Address Byte
HDLC Controller
Message Transfer Modes
HDLC Controller Address Range
FIFO Address
00
H
-1F
C/R 0
H
102
TEI 1, 2, TEIG
Low Address Byte
H
Description of Functional Blocks
-1F
Config/Ctrl/Status Registers
20
H
H
is used (similar as in ISAC-S
-29
H
EA
ISAC-SX TE
PSB 3186
2003-01-30