PEF24902HV21XP Lantiq, PEF24902HV21XP Datasheet - Page 36

• Manufacturer Part Number: PEF24902HV21XP
• Manufacturer: Lantiq

Specifications of PEF24902HV21XP

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Compliant

Table 14
Boundary Scan
Number
TDI ––>
6
7
8
9
10
11
TAP Controller
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG standard IEEE Std. 1149.1. Transitions on the pin TMS cause the TAP controller
to perform a state change.
The following instructions are executable.
Table 15
Code
000
001
010
011
11X
EXTEST is used to examine the board interconnections.
When the TAP controller is in the state "update DR", all output pins are updated with the
falling edge of TCK. When it has entered state "capture DR" the levels of all input pins
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
INTEST supports internal chip testing.
When the TAP controller is in the state "update DR", all inputs are updated internally with
the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
Note: 001 (INTEST) is the default value of the instruction register.
Data Sheet
Instruction
EXTEST
INTEST
SAMPLE/PRELOAD
IDCODE
BYPASS
Sequence of Pins in the Boundary Scan (cont’d)
TAP Controller Instructions
Pin
Number
26
27
38
39
40
41
Pin Name
CLOCK
DIN
PDM0
PDM1
PDM2
SDR
External testing
Snap-shot testing
Bypass operation
Function
Internal testing
Reading ID code
36
Type
I
I
O
O
O
O
Number of
Scan Cells
1
1
2
2
2
2
Functional Description
Rev. 1, 2004-05-28
Default
value
TDI ––>
0
0
0 0
0 0
1 0
0 1
PEB 24902
PEF 24902