PEF24902HV21XP Lantiq, PEF24902HV21XP Datasheet - Page 32

• Manufacturer Part Number: PEF24902HV21XP
• Manufacturer: Lantiq

Specifications of PEF24902HV21XP

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Compliant

SY:
"0":
3.4.1
The 192 available bits during a 80 kHz period (related to the 15.36 MHz clock) are
divided into the 9 slots of which 8 slots are 21 bits long used for data transmission.
The status on SDR is synchronized to SDX. Each time slot on SDR carries the
corresponding LD bit during the last 20 bits of the slot.
Figure 8
The 2B1Q data is coded with the bits TD2, TD1, TD0:
Table 11
2B1Q Data
0
– 3
– 1
+ 3
+ 1
3.4.2
The 128 available bits during a 120 kHz period (related to the 15.36 MHz clock) are
divided into 9 slots of which 8 slots are 13 bits long used for data transmission. The
status on SDR is synchronized to SDX. Each time slot on SDR carries the corresponding
LD bit during the last 12 bits of the slot.
Data Sheet
SDR
SDX
0
SY=1
0
0
21 Bit
Slot 0
TD 2
First bit of the time slots with transmission data. For synchronization and bit
allocation on SDX and SDR, SY is set to ONE.
Reserved bit. Reserved bits are currently not defined and shall be set to
ZERO. Some of these bits may be used for test purposes or can be assigned
a function in later versions.
LD
1
Frame Structure on the Digital Interface in the 2B1Q Mode
Frame Structure on the Digital Interface in the 4B3T Mode
21
TD 1
Frame Structure on SDX and SDR in 2B1Q Mode
Coding of the 2B1Q Data Pulse (AOUTx/BOUTx)
21 Bit
Slot 1
2
TD 0
3
42
NOPQ
21 Bit
Slot 2
TD2
„1“
0
0
0
0
4
PDOW LOOP RANGE
5
63
21 Bit
Slot 3
6
7
84
21 Bit
Slot 4
NT
8
"0"
9
105
32
Slot 5
21 Bit
TD1
„don´t care“
0
0
1
1
"0"
10
11
"0"
126
21 Bit
Slot 6
"0"
12
13
147
"0"
Slot 7
21 Bit
"0"
14
168
Functional Description
Synch. Word
15
"0"
24 Bit
TD0
„don´t care“
0
1
0
1
"0"
16
Rev. 1, 2004-05-28
191
17
"0"
PEB 24902
18
PEF 24902
"0"
19
"0"
ITD07142.vsd
20
"0"