PEB20591HV22XP Lantiq, PEB20591HV22XP Datasheet - Page 43

• Manufacturer Part Number: PEB20591HV22XP
• Manufacturer: Lantiq

Specifications of PEB20591HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY
INTEST . INTEST supports internal chip testing.
When the TAP controller is in the state “update DR”, all inputs are updated internally with
the falling edge of TCK. When it has entered state “capture DR” the levels of all outputs
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
Note: 0011 (IDCODE) is the default value of the instruction register.
SAMPLE/PRELOAD. SAMPLE/PRELOAD provides a snap-shot of the pin level during
normal operation or is used to either preload (TDI) or shift out (TDO) the boundary scan
test vector. Both activities are transparent to the system functionality.
Note: The input pin CLK15-I should not be evaluated.
IDCODE. The 32-bit identification register is read out serially via TDO. It contains the
version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits).
The LSB is fixed to ’1’.
The code for VIP version 2.1 is ’0010’.
Note: In the state “test logic reset”, the code “0011” is loaded into the instruction code
BYPASS. A bit entering TDI is shifted to TDO after one TCK clock cycle, e.g. to skip
testing of selected ICs on a printed circuit board.
User-Specific Instructions. Symmetric continuous pulses can be generated at pins
LIna/b (60 kHz) and SXna/b (120 kHz) to test the analog line interfaces.
Note: A 15.36 MHz crystal or an external 15.36 MHz clock signal on CLK15-I is required
Data Sheet
Version
0010
The input frequency (15.36 MHz) is not synchronous with TCK (6.25 MHz); this
may cause unpredictable snap-shots on the pin CLK15-I.
register.
for test pulse generation.
Device Code
0000 0000 0100 1111
35
Manufacturer Code
0000 1000 001
Interface Description
1
PEB 20590
PEB 20591
2001-03-01
Output
--> TDO