PEB20591HV22XP Lantiq, PEB20591HV22XP Datasheet - Page 40

• Manufacturer Part Number: PEB20591HV22XP
• Manufacturer: Lantiq

Specifications of PEB20591HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY
Data Sheet
Figure 21
Note: 1. Data transfer on IOM-2000 interface always starts with the MSB (related to B
2. All registers follow the Intel structure (LSB=2
3. Unused bits are don’t care (’x’)
4. The order of reception or transmission of each VIP channel is always
Ch0,2,4,6 in U
Ch1,3,5,7 in S mode (LT-S)
DX/DR
FSC
DCL
channels), whereas CMD and STAT bits transfer always starts with LSB (bit 0)
of any register
channel 0 to channel 7. A freely programmable channel assignment of multiple
VIPs on IOM-2000 (e.g., ch0 of VIP_0, ch1 of VIP_0, ch0 of VIP_1, ch2 of
VIP_0,...) is not possible.
F-bit
IOM-2000 Data Sequence (1 VIP with 8 Channels)
Ch0 bit0
PN
mode
Ch1 bit0 (data)
Ch2 bit0
Ch7 bit0 (data)
Ch0 bit1
last bit of U
Ch1 bit0 (ctrl)
Ch2 bit1
3.072 MHz
Ch7 bit0 (ctrl)
125 µs
PN
Ch0 bit2
last bit of LT-S frame
frame
32
Ch1 bit1 (data)
LT-S mode:
U
Ch2 bit2
PN
mode:
Ch7 bit1 (data)
0
, MSB=2
data ctrl
data
31
Interface Description
Ch6 bit37
)
PEB 20590
PEB 20591
Ch7 bit 23 (ctrl)
2001-03-01