PEB20591HV22XP Lantiq, PEB20591HV22XP Datasheet - Page 22

• Manufacturer Part Number: PEB20591HV22XP
• Manufacturer: Lantiq

Specifications of PEB20591HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY
Table 5
Pin
No.
42
43
17
33
34
16
41
5
60
Data Sheet
Symbol
CLK15-I
CLK15-O
INCLK
VIP_ADD0
VIP_ADD1
IDDQ
POWDN
DIR
SCANEN
Clock Signals and Dedicated Pins
In (I)
Out (O)
I
O
I
I
I
I
O
I
During
Reset
I
O
I
I
I
I
O
I
Function
15.36-MHz External Crystal Input
15.36-MHz External Crystal Output
External Reference CLocK INput
Reference clock from VIP or Central Office
VIP ADDress Pins
Determines the sequential order of up to
3 VIPs in the IOM-2000 frame for the 12-
MHz case:
VIP_ADD(1:0)
’00’ = VIP in 1st quarter of IOM-2000 frame
’01’ = VIP in 2nd quarter of IOM-2000 frame
’10’ = VIP in 3rd quarter of IOM-2000 frame
’11’ = Reserved for future connection of VIP
in 4th quarter of IOM-2000 frame. Currently
only the lower addresses are available.
(refer to IOM-2000 description in DELIC-LC/
-PB Data Sheet)
IDDQ Test Mode
Forces the Line Interface Unit into power
down mode for IDDQ testing.
Oscillator POWer DowN
Switches the internal oscillator into power
down mode (in case that 15.36-MHz input
clock is provided by the DELIC)
DIRection of Transfer on U
Indicates the direction of the data transfer
(Tx or Rx) in U
for driving electronic transformers).
SCAN ENable
If driven to ’1’ during device tests, a full scan
of the VIP is enabled.
14
PN
ping-pong mode (required
PN
Pin Description
Line Interface
PEB 20590
PEB 20591
2001-03-01