ispPAC-POWR1220AT8-01T100I Lattice, ispPAC-POWR1220AT8-01T100I Datasheet - Page 40

• Manufacturer Part Number: ispPAC-POWR1220AT8-01T100I
• Description: Supervisory Circuits Prec Prg Pwr Spply S eq. Mon. Mrg Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1220AT8-01T100I

• Number Of Voltages Monitored: 12
• Undervoltage Threshold: 0.8 V
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 40 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 40mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
SMBus SMBAlert Function
The ispPAC-POWR1220AT8 provides an SMBus SMBAlert function so that it can request service from the bus
master when it is used as part of an SMBus system. This feature is supported as an alternate function of OUT5.
When the SMBAlert feature is enabled, OUT5 is controlled by a combination of the PLD ORP and the GP5_ENb bit
(Figure 1-31). Note: To enable the SMBAlert feature, the SMB_Mode (EECMOS bit) should be set in software.
Figure 1-31. ispPAC-POWR1220AT8 SMBAlert Logic
The typical flow for an SMBAlert transaction is as follows (Figure 1-31):
Figure 1-32. SMBAlert Bus Transaction
After OUT5/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service
functions in which it may send data to or read data from the ispPAC-POWR1220AT8. As part of the service func-
tions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also
need to reset GP5_ENb to re-enable the SMBAlert function. For further information on the SMBus, the user should
consult the SMBus Standard.
SMBA
1. GP5_ENb bit is forced (Via I
2. ispPAC-POWR1220AT8 PLD Logic pulls OUT5/SMBA Low
3. Master responds to interrupt from SMBA line
4. Master broadcasts a read operation using the SMBus Alert Response Address (ARA)
5. ispPAC-POWR1220AT8 responds to read request by transmitting its device address
6. If transmitted device address matches ispPAC-POWR1220AT8 address, it sets GP5_ENb bit high. 
SDA
SCL
This releases OUT5/SMBA.
ASSERTS
SLAVE
SMBA
Routing
Output
Pool
PLD
START
I 2 C Interface Unit
PLD Output/GP_Output Register Select
0
1
GP5_ENb
0
2
(E 2 Configuration)
2
ALERT RESPONSE ADDRESS
C write) to Low
0
3
MUX
1
4
(0001 100)
1
5
0
6
7
0
R/W
SMBAlert
8
1-40
Logic
OUT5/SMBA Mode Select
ACK
9
(E 2 Configuration)
A6
1
MUX
A5
2
ispPAC-POWR1220AT8 Data Sheet
A4
SLAVE ADDRESS (7 BITS)
3
A3
4
A2
5
A1
6
OUT5/SMBA
A0
7
Note: Shaded Bits Asserted by Slave
8
x
ACK
9
RELEASES
SLAVE
SMBA
STOP