ispPAC-POWR1220AT8-01T100I Lattice, ispPAC-POWR1220AT8-01T100I Datasheet - Page 39
![Supervisory Circuits Prec Prg Pwr Spply S eq. Mon. Mrg Trim I](/photos/16/2/160258/tqfp-100_sml.jpg)
ispPAC-POWR1220AT8-01T100I
Manufacturer Part Number
ispPAC-POWR1220AT8-01T100I
Description
Supervisory Circuits Prec Prg Pwr Spply S eq. Mon. Mrg Trim I
Manufacturer
Lattice
Series
ispPAC®r
Datasheet
1.ISPPAC-POWR1220AT8-02TN100I.pdf
(54 pages)
Specifications of ispPAC-POWR1220AT8-01T100I
Number Of Voltages Monitored
12
Undervoltage Threshold
0.8 V
Output Type
Open Collector / Drain
Manual Reset
Not Resettable
Watchdog
No Watchdog
Power-up Reset Delay (typ)
500 ms
Supply Voltage (max)
3.96 V
Supply Voltage (min)
2.8 V
Supply Current (typ)
40 mA
Mounting Style
SMD/SMT
Package / Case
TQFP-100
Applications
General Purpose
Voltage - Input
-0.3 V ~ 5.9 V
Voltage - Supply
2.8 V ~ 3.96 V
Current - Supply
40mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISPPAC-POWR1220AT8-01T100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
The ispPAC-POWR1220AT8 also provides the user with the ability to program the trim values over the I
by writing the appropriate binary word to the associated trim register (Figure 1-30).
Figure 1-30. I
2
C Trim Registers
0x13 - TRIM1_TRIM (Read/Write)
0x14 - TRIM2_TRIM (Read/Write)
0x15 - TRIM3_TRIM (Read/Write)
0x16 - TRIM4_TRIM (Read/Write)
0x17 - TRIM5_TRIM (Read/Write)
0x18 - TRIM6_TRIM (Read/Write)
0x19 - TRIM7_TRIM (Read/Write)
0x1A - TRIM8_TRIM (Read/Write)
D7
D7
D7
D7
D7
D7
D7
D7
b7
b7
b7
b7
b7
b7
b7
b7
D6
D6
D6
D6
D6
D6
D6
D6
b6
b6
b6
b6
b6
b6
b6
b6
D5
D5
D5
D5
D5
D5
D5
D5
b5
b5
b5
b5
b5
b5
b5
b5
D4
D4
D4
D4
D4
D4
D4
D4
b4
b4
b4
b4
b4
b4
b4
b4
1-39
D3
D3
D3
D3
D3
D3
D3
D3
b3
b3
b3
b3
b3
b3
b3
b3
ispPAC-POWR1220AT8 Data Sheet
D2
D2
D2
D2
D2
D2
D2
D2
b2
b2
b2
b2
b2
b2
b2
b2
D1
D1
D1
D1
D1
D1
D1
D1
b1
b1
b1
b1
b1
b1
b1
b1
D0
D0
D0
D0
D0
D0
D0
D0
b0
b0
b0
b0
b0
b0
b0
b0
2
C interface,