PAC-POWR1220AT8-HS-EVN Lattice, PAC-POWR1220AT8-HS-EVN Datasheet - Page 30

• Manufacturer Part Number: PAC-POWR1220AT8-HS-EVN
• Description: Supervisory Circuits Pwr Mgr Hercules Std Development Kit
• Manufacturer: Lattice
• Series: ispPAC®, MachXO, Herculesr

Specifications of PAC-POWR1220AT8-HS-EVN

• Silicon Manufacturer: Lattice Semiconductor
• Kit Application Type: Power Management
• Application Sub Type: Power Manager
• Kit Contents: Preloaded Board, Eval Board, AC Adapter, USB Connector Cable
• Rohs Compliant: Yes
• Main Purpose: Power Management, ORing Controller / Hot Swap Controller
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR1220AT8, LCMXO2280
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 1-7. Output DAC Update Rate in Digital Closed Loop Mode
There is a one-to-one relationship between the selected TrimCell and the corresponding VMON input for the closed
loop operation. For example, if TrimCell 3 is used to control the power supply in the closed loop trim mode, VMON3
must be used to monitor its output power supply voltage.
The closed loop operation can only be started by activating the internally generated PLD signal, called
PLD_CLT_EN, in PAC-Designer software. The selection of Voltage Profile 0, however, can be either through the
pins VPS0, VPS1 or through the PLD signals PLDVPS0 and PLDVPS1.
Closed Loop Start-up Behavior
The contents of the closed loop register, upon power-up, will contain a value 80h (Bipolar-zero) value. The DAC
output voltage will be equal to the programmed Offset voltage. Usually under this condition, the power supply out-
put will be close to its nominal voltage. If the power supply trimming should start after reaching its desired output
voltage, the corresponding DAC code can be loaded into the closed loop trim register through I
as the DAC register I
Details of the Digital to Analog Converter (DAC)
Each trim cell has an 8-bit bipolar DAC to set the trimming voltage (Figure 1-20). The full-scale output voltage of
the DAC is +/- 320 mV. A code of 80H results in the DAC output set at its bi-polar zero value.
The voltage output from the DAC is added to a programmable offset value and the resultant voltage is then applied
to the trim output pin. The offset voltage is typically selected to be approximately equal to the DC-DC converter
open circuit trim node voltage. This results in maximizing the DC-DC converter output voltage range.
The programmed offset value can be set to 0.6V, 0.8V, 1.0V or 1.25V. This value selection is stored in E
memory and cannot be changed dynamically.
Figure 1-20. Offset Voltage is Added to DAC Output Voltage to Derive Trim Pad Voltage
Trim Registers
From
2
C mode) before activating the PLD_CLT_EN signal.
8
(-320mV to +320mV)
7 bits + Sign
DAC
Control Value
Update Rate
(0.6V,0.8V,1.0V,1.25V)
00
01
10
11
E2CMOS
Offset
1-30
Interval
1.15 ms
9.22 ms
18.5 ms
Update
580 µs
ispPAC-POWR1220AT8 Data Sheet
TRIMCELL X
TRIMx
2
Pad
C (same address
2
CMOS