MD1711K6-G Supertex, MD1711K6-G Datasheet - Page 9

• Manufacturer Part Number: MD1711K6-G
• Description: MOSFET & Power Driver ICs MOSFET HI SPD INTEGR ULTRASND DRVR
• Manufacturer: Supertex
• Type: High Speedr

Specifications of MD1711K6-G

• Rise Time: 8 ns
• Fall Time: 8 ns
• Supply Voltage (min): 1.8 V
• Supply Current: 2 mA
• Maximum Power Dissipation: 1200 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Number Of Drivers: 12
• Number Of Outputs: 12
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pin Description (48-Lead LQFP & 48-Lead QFN)
Pin #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
HVEN2B / NEG2B
HVEN1A / POS2A
HVEN2A / NEG2A
HVEN1B / POS2B
NEGB / NEG1B
NEGA / NEG1A
POSB / POS1B
POSA / POS1A
OUT-NB1
OUT-PB3
OUT-PB2
OUT-PB1
CLAMPB
CLAMPA
AGND
DGND
DV
DV
DV
Name
AV
DV
AV
SEL
N/C
DD
DD
DD
DD
SS
SS
1
1
2
2
Description
Logic input control for channel A. When SEL = L, the pin is POSA. When SEL = H, the pin
is POS1A.
Logic input control for channel A. When SEL = L, the pin is NEGA. When SEL = H, the pin
is NEG1A.
Logic input control for channel A. When SE L= L, the pin is HVEN1A. When SEL = H, the
pin is POS2A.
Logic input control for channel A. When SEL = L, the pin is HVEN2A. When SEL = H, the
pin is NEG2A.
Used with SEL = H. Logic input control for OUT-PA3 and OUT-NA3. Connect to ground when
SEL = L.
Supplies analog circuitry portion of the gate driver. Should be at the same potential as
DV
Analog Ground.
Used with SEL = H. Logic input control for OUT-PB3 and OUT-NB3. Connect to ground when
SEL = L.
Logic input control for channel B. When SEL = L, the pin is HVEN2B. When SEL = H, the
pin is NEG2B.
Logic input control for channel B. When SEL = L, the pin is HVEN1B. When SEL = H, the
pin is POS2B.
Logic input control for channel B. When SEL = L, the pin is NEGB. When SEL = H, the pin
is NEG1B.
Logic input control for channel B. When SEL = L, the pin is POSB. When SEL = H, the pin
is POS1B.
Logic input select. See truth tables for SEL = L and SEL = H.
Negative driver supply for OUT-PA3, OUT-PB3 and bias circuits. They are also connected
to the IC substrate. They are required to connect to the most negative potential of voltage
supplies.
Gate drive supply voltage for OUT-PA3 and OUT-PB3. Supplies digital circuitry portion and
the main Output stage. Should be at the same potential as AVSS.
Output P-Channel gate driver for channel B
Digital Ground.
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA2, OUT-NA2, OUT-NA3, OUT-PB2, OUT-NB2, and OUT-NB3. hould
be at the same potential as AV
Output P-Channel gate driver for channel B
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different po-
tential than DV
Output P-Channel gate driver for channel B
No connect.
Output N-Channel gate driver for channel B
Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main
output stage for OUT-PA1, OUT-NA1, OUT-PB1, and OUT-NB1. Can be at a different po-
tential than DV
DD
1.
DD
DD
1.
1.
DD
9
1.
MD1711