ICS1893BFILFT IDT, Integrated Device Technology Inc, ICS1893BFILFT Datasheet - Page 86

PHYCEIVER LOW PWR 3.3V 48-SSOP

ICS1893BFILFT

Manufacturer Part Number
ICS1893BFILFT
Description
PHYCEIVER LOW PWR 3.3V 48-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Datasheets

Specifications of ICS1893BFILFT

Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
48-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
1893BFILFT
7.13.8 Link Loss Inhibit (bit 18.1)
7.13.9 Squelch Inhibit (bit 18.0)
ICS1893BF, Rev. E, 8/11/09
The Link Loss Inhibit bit allows an STA to prevent the ICS1893BF from dropping the link in 10Base-T mode.
When an STA sets this bit to logic:
The Squelch Inhibit bit allows an STA to control the ICS1893BF Squelch Detection in 10Base-T mode.
When an STA sets this bit to logic:
Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted-
Pair Receiver inputs.
One, the ICS1893BF 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state
regardless of the Twisted-Pair Receiver input conditions.
Zero, before the ICS1893BF can establish a valid link, the ICS1893BF must receive valid 10Base-T
data.
One, before the ICS1893BF can establish a valid link, the ICS1893BF must receive both valid 10Base-T
data followed by an IDL.
ICS1893BF Data Sheet - Release
Copyright © 2009, IDT, Inc.
All rights reserved.
86
Chapter 7 Management Register Set
August, 2009

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