PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 178

• Manufacturer Part Number: PIC16F726-I/SP
• Description: 28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F726-I/SP

• A/d Inputs: 11-Channel, 8-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 20 MHz
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: I2C, SPI, AUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F72X/PIC16LF72X
17.2.2
During times of no data transfer (Idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through external pull-up resistors. The Start and Stop
conditions determine the start and stop of data trans-
mission. The Start condition is defined as a high-to-low
transition of the SDA line while SCL is high. The Stop
condition is defined as a low-to-high transition of the
SDA line while SCL is high.
FIGURE 17-9:
17.2.3
After the valid reception of an address or data byte, the
hardware automatically will generate the Acknowledge
(ACK) pulse and load the SSPBUF register with the
received value currently in the SSPSR register. There
are certain conditions that will cause the SSP module
not to generate this ACK pulse. They include any or all
of the following:
• The Buffer Full bit, BF of the SSPSTAT register,
• The SSP Overflow bit, SSPOV of the SSPCON
• The SSP Module is being operated in Firmware
TABLE 17-2:
DS41341B-page 176
Note 1:
was set before the transfer was received.
register, was set before the transfer was received.
Master mode.
Transfer is Received
Status Bits as Data
BF
0
1
1
0
SDA
SCL
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
START AND STOP CONDITIONS
ACKNOWLEDGE
SSPOV
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
START AND STOP CONDITIONS
Condition
Start
S
SSPSR → SSPBUF
Data Allowed
Change of
Yes
No
No
No
Preliminary
Figure 17-9 shows the Start and Stop conditions. A
master device generates these conditions for starting
and terminating data transfer. Due to the definition of
the Start and Stop conditions, when data is being trans-
mitted, the SDA line can only change state when the
SCL line is low.
In such a case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. Table 17-2 shows the results of when a data
transfer byte is received, given the status of bits BF and
SSPOV. Flag bit BF is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
Generate ACK
Pulse
Yes
No
No
No
Data Allowed
Change of
© 2008 Microchip Technology Inc.
(SSP Interrupt occurs
Condition
Stop
Set bit SSPIF
P
if enabled)
Yes
Yes
Yes
Yes