PIC16F818-I/P Microchip Technology Inc., PIC16F818-I/P Datasheet - Page 98

• Manufacturer Part Number: PIC16F818-I/P
• Description: 18 PIN, 1.75 KB FLASH, 128 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F818-I/P

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F818/819
FIGURE 12-6:
12.10 Interrupts
The PIC16F818/819 has up to nine sources of inter-
rupt. The Interrupt Control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-7:
DS39598E-page 96
Note:
PWRT Time-out
Individual interrupt flag bits are set
regardless
corresponding mask bit or the GIE bit.
OST Time-out
Internal Reset
TMR2IF
TMR2IE
Internal POR
EEIF
EEIE
ADIF
ADIE
MCLR
CCP1IF
CCP1IE
TMR1IF
TMR1IE
SSPIF
SSPIE
V
DD
SLOW RISE TIME (MCLR TIED TO V
INTERRUPT LOGIC
of
the
status
0V
T
PWRT
of
their
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
1V
5V
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the
Special Function Register, PIR1. The corresponding
interrupt enable bits are contained in Special Function
Register, PIE1 and the peripheral interrupt enable bit is
contained in Special Function Register, INTCON.
When an interrupt is serviced, the GIE bit is cleared to
disable any further interrupt, the return address is
pushed onto the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs relative to
the current Q cycle. The latency is the same for one or
two-cycle instructions. Individual interrupt flag bits are
set regardless of the status of their corresponding
mask bit, PEIE bit or the GIE bit.
DD
THROUGH RC NETWORK)
T
OST
Wake-up (if in Sleep mode)
 2004 Microchip Technology Inc.
Interrupt to CPU