PIC16F818-I/P Microchip Technology Inc., PIC16F818-I/P Datasheet - Page 102

• Manufacturer Part Number: PIC16F818-I/P
• Description: 18 PIN, 1.75 KB FLASH, 128 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F818-I/P

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F818/819
FIGURE 12-9:
12.14 In-Circuit Debugger
When the DEBUG bit in the Configuration Word is
programmed to a ‘0’, the In-Circuit Debugger function-
ality is enabled. This function allows simple debugging
functions when used with MPLAB
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 12-6
shows which features are consumed by the background
debugger.
TABLE 12-6:
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/V
RB7 and RB6. This will interface to the in-circuit
debugger module available from Microchip or one of
the third party development tool companies.
DS39598E-page 100
I/O pins
Stack
Program Memory
Data Memory
Note
OSC1
CLKO
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Instruction
Executed
(4)
1:
2:
3:
4:
PC
XT, HS or LP Oscillator mode assumed.
T
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
CLKO is not available in these oscillator modes but shown here for timing reference.
OST
Inst(PC) = Sleep
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC – 1)
= 1024 T
DEBUGGER RESOURCES
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
0x070 (0x0F0, 0x170, 0x1F0)
Address 0000h must be NOP
(drawing not to scale). This delay will not be there for RC Oscillator mode.
Last 100h words
Inst(PC + 1)
0x1EB-0x1EF
Sleep
PC + 1
RB6, RB7
1 level
®
ICD. When the
PP
, V
Processor in
DD
Sleep
, GND,
PC + 2
T
OST (2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
12.15 Program Verification/Code
If
programmed, the on-chip program memory can be
read out for verification purposes.
12.16 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. It is
recommended that only the four Least Significant bits
of the ID location are used.
PC + 2
the
Protection
code
Interrupt Latency
Dummy Cycle
(Note 2)
PC + 2
protection
 2004 Microchip Technology Inc.
Dummy Cycle
Inst(0004h)
0004h
bit(s)
have
Inst(0005h)
Inst(0004h)
0005h
not
been