PIC16F818-I/P Microchip Technology Inc., PIC16F818-I/P Datasheet - Page 100

• Manufacturer Part Number: PIC16F818-I/P
• Description: 18 PIN, 1.75 KB FLASH, 128 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F818-I/P

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F818/819
12.12 Watchdog Timer (WDT)
For PIC16F818/819 devices, the WDT is driven by the
INTRC oscillator. When the WDT is enabled, the
INTRC (31.25 kHz) oscillator is enabled. The nominal
WDT period is 16 ms and has the same accuracy as
the INTRC oscillator.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog
Timer wake-up). The TO bit in the Status register will be
cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing con-
figuration bit, WDTEN (see Section 12.1 “Configuration
Bits”).
FIGURE 12-8:
TABLE 12-5:
DS39598E-page 98
81h,181h OPTION_REG
2007h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1:
Address
Configuration bits
See Register 12-1 for operation of these bits.
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
Enable Bit
31.25 kHz
INTRC
WDT
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
(1)
RBPU
Bit 7
LVP
0
1
INTEDG
BOREN
Bit 6
PSA
M
U
X
MCLRE
T0CS
Bit 5
0
Time-out
WDT time-out period values may be found in
Section 15.0 “Electrical Characteristics” under
parameter #31. Values for the WDT prescaler (actually
a postscaler but shared with the Timer0 prescaler) may
be assigned using the OPTION_REG register.
MUX
WDT
FOSC2
8-to-1 MUX
T0SE
Postscaler
Bit 4
Note 1: The CLRWDT and SLEEP instructions
1
8
2: When a CLRWDT instruction is executed
PWRTEN
clear the WDT and the postscaler if
assigned to the WDT and prevent it from
timing out and generating a device Reset
condition.
and the prescaler is assigned to the WDT,
the prescaler count will be cleared but the
prescaler assignment is not changed.
Bit 3
PSA
PSA
To TMR0 (Figure 6-1)
PS2:PS0
WDTEN
 2004 Microchip Technology Inc.
Bit 2
PS2
FOSC1
Bit 1
PS1
FOSC0
Bit 0
PS0