PIC16F818-I/P Microchip Technology Inc., PIC16F818-I/P Datasheet - Page 29

• Manufacturer Part Number: PIC16F818-I/P
• Description: 18 PIN, 1.75 KB FLASH, 128 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F818-I/P

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.3
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available in the very next
cycle in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read or until it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1.
2.
3.
4.
EXAMPLE 3-1:
3.4
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then, the user must follow a
specific write sequence to initiate the write for each
byte.
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
 2004 Microchip Technology Inc.
BANKSEL EEADR
MOVF
MOVWF
BANKSEL EECON1
BCF
BSF
BANKSEL EEDATA
MOVF
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the RD bit to start the read operation.
Read the data from the EEDATA register.
Reading Data EEPROM Memory
Writing to Data EEPROM Memory
ADDR, W
EEADR
EECON1, EEPGD ; Point to Data memory
EECON1, RD
EEDATA, W
DATA EEPROM READ
; Select Bank of EEADR
;
; Data Memory Address
; to read
; Select Bank of EECON1
; EE Read
; Select Bank of EEDATA
; W = EEDATA
The steps to write to EEPROM data memory are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. At the completion of the write cycle, the WR bit
EXAMPLE 3-2:
If step 10 is not implemented, check the WR bit
to see if a write is in progress.
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
Write the 8-bit data value to be programmed in
the EEDATA register.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the WREN bit to enable program operations.
Disable interrupts (if enabled).
Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first to W,
• Write AAh to EECON2 in two steps (first to W,
• Set the WR bit
Enable interrupts (if using interrupts).
Clear the WREN bit to disable program
operations.
is cleared and the EEIF interrupt flag bit is set
(EEIF must be cleared by firmware). If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to be clear, to indicate
the end of the program cycle.
BANKSEL EECON1
BTFSC
GOTO
BANKSEL EEADR
MOVF
MOVWF
MOVF
MOVWF
BANKSEL EECON1
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
then to EECON2)
then to EECON2)
EECON1, WR
$-1
ADDR, W
EEADR
VALUE, W
EEDATA
EECON1, EEPGD ; Point to DATA
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
PIC16F818/819
DATA EEPROM WRITE
; Select Bank of
; EECON1
; Wait for write
; to complete
; Select Bank of
; EEADR
;
; Data Memory
; Address to write
;
; Data Memory Value
; to write
; Select Bank of
; EECON1
; memory
; Enable writes
; Disable INTs.
;
; Write 55h
;
; Write AAh
; Set WR bit to
; begin write
; Enable INTs.
; Disable writes
DS39598E-page 27