DSPIC30F3012-30I/P Microchip Technology Inc., DSPIC30F3012-30I/P Datasheet - Page 50
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
DSPIC30F3012-30I/P
Manufacturer Part Number
DSPIC30F3012-30I/P
Description
16 BIT MCU/DSP 18LD 30MIPS 24 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F3012-30IP.pdf
(204 pages)
Specifications of DSPIC30F3012-30I/P
A/d Inputs
8-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
12
Interface
I2C/SPI/UART, USART
Ios
12
Memory Type
Flash
Number Of Bits
16
Package Type
18-pin PDIP
Programmable Memory
24K Bytes
Ram Size
2K Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F3012-30I/P
Manufacturer:
Microchip Technology
Quantity:
1 936
Company:
Part Number:
DSPIC30F3012-30I/P
Manufacturer:
TI
Quantity:
6
Part Number:
DSPIC30F3012-30I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F3012-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F2011/2012/3012/3013
5.4
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions or 96 bytes. Each panel consists of 128 rows or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program four
instructions at one time. RTSP may be used to program
multiple program memory panels, but the Table Pointer
must be changed at each panel boundary.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The instruction words loaded must always be from
a 32 address boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and four TBLWTH instructions are required to
load the 32 instructions. If multiple panel programming
is required, the Table Pointer needs to be changed and
the next set of multiple write latches written.
All of the table write operations are single-word writes
(2 instruction cycles), because only the table latches
are written. A programming cycle is required for
programming each row.
The Flash Program Memory is readable, writable and
erasable during normal operation over the entire V
range.
DS70139D-page 48
RTSP Operation
DD
5.5
The four SFRs used to read and write the program
Flash memory are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
5.5.1
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed, and
start of the programming cycle.
5.5.2
The NVMADR register is used to hold the lower two
bytes of the Effective Address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
5.5.3
The NVMADRU register is used to hold the upper byte
of the Effective Address. The NVMADRU register cap-
tures the EA<23:16> of the last table instruction that
has been executed.
5.5.4
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.6
“Programming Operations” for further details.
Note:
Control Registers
NVMCON REGISTER
NVMADR REGISTER
NVMADRU REGISTER
NVMKEY REGISTER
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
© 2006 Microchip Technology Inc.