DSPIC30F3012-30I/P Microchip Technology Inc., DSPIC30F3012-30I/P Datasheet - Page 199
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DSPIC30F3012-30I/P
Manufacturer Part Number
DSPIC30F3012-30I/P
Description
16 BIT MCU/DSP 18LD 30MIPS 24 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F3012-30IP.pdf
(204 pages)
Specifications of DSPIC30F3012-30I/P
A/d Inputs
8-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
12
Interface
I2C/SPI/UART, USART
Ios
12
Memory Type
Flash
Number Of Bits
16
Package Type
18-pin PDIP
Programmable Memory
24K Bytes
Ram Size
2K Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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Timing Specifications
Trap Vectors ....................................................................... 67
U
UART Module
UART Operation
Unit ID Locations............................................................... 119
Universal Asynchronous Receiver Transmitter
W
Wake-up from Sleep ......................................................... 119
Wake-up from Sleep and Idle ............................................. 68
Watchdog Timer
Watchdog Timer (WDT) ............................................ 119, 129
WWW Address.................................................................. 199
WWW, On-Line Support ....................................................... 7
© 2006 Microchip Technology Inc.
Input Capture ............................................................ 165
Oscillator Start-up Timer ........................................... 161
Output Compare Module........................................... 166
Power-up Timer ........................................................ 161
Reset......................................................................... 161
Simple OC/PWM Mode............................................. 167
SPI Module
Type A Timer External Clock .................................... 163
Type B Timer External Clock .................................... 164
Type C Timer External Clock .................................... 164
Watchdog Timer........................................................ 161
PLL Clock.................................................................. 157
Address Detect Mode ............................................... 105
Auto-Baud Support ................................................... 106
Baud Rate Generator................................................ 105
Enabling and Setting Up ........................................... 103
Framing Error (FERR)............................................... 105
Idle Status ................................................................. 105
Loopback Mode ........................................................ 105
Operation During CPU Sleep and Idle Modes .......... 106
Overview ................................................................... 101
Parity Error (PERR) .................................................. 105
Receive Break........................................................... 105
Receive Buffer (UxRXB) ........................................... 104
Receive Buffer Overrun Error (OERR Bit) ................ 104
Receive Interrupt....................................................... 104
Receiving Data.......................................................... 104
Receiving in 8-bit or 9-bit Data Mode........................ 104
Reception Error Handling.......................................... 104
Transmit Break.......................................................... 104
Transmit Buffer (UxTXB)........................................... 103
Transmit Interrupt...................................................... 104
Transmitting Data...................................................... 103
Transmitting in 8-bit Data Mode................................ 103
Transmitting in 9-bit Data Mode................................ 103
UART1 Register Map................................................ 107
UART2 Register Map................................................ 107
Idle Mode .................................................................. 106
Sleep Mode............................................................... 106
(UART) Module ......................................................... 101
Timing Characteristics .............................................. 161
Timing Requirements................................................ 161
Enabling and Disabling ............................................. 129
Operation .................................................................. 129
Master Mode (CKE = 0) .................................... 168
Master Mode (CKE = 1) .................................... 169
Slave Mode (CKE = 0) ...................................... 170
Slave Mode (CKE = 1) ...................................... 172
dsPIC30F2011/2012/3012/3013
DS70139D-page 197