DS26521L+ Maxim Integrated Products, DS26521L+ Datasheet - Page 76

• Manufacturer Part Number: DS26521L+
• Description: IC TXRX T1/E1/J1 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26521L+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 220 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.11.4 Jitter Attenuator
The DS26521 contains a jitter attenuator for each LIU that can be set to a depth of 32 or 128 bits via the JADS
(LTRCR.4) bit in the LIU Transmit Receive Control register (LTRCR).
The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used
in delay-sensitive applications. The characteristics of the attenuation are shown in
can be placed in either the receive path, the transmit path, or disabled by appropriately setting the JAPS1 and
JAPS0 bits in LTRCR.
For the jitter attenuator to operate properly, a 2.048MHz, 1.544MHz, or a multiple of up to 8x clock must be applied
at MCLK. See the Global Transceiver Clock Control register (GTCCR) for MCLK options. ITU-T specification G.703
requires an accuracy of ±50ppm for both T1/J1 and E1 applications. TR62411 and ANSI specs require an accuracy
of ±32ppm for T1/J1 interfaces. Circuitry adjusts either the recovered clock from the clock/data recovery block or
the clock applied at the TCLK pin to create a smooth jitter-free clock, which is used to clock data out of the jitter
attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed in
the transmit side. If the incoming jitter exceeds either 120UI
32 bits), the DS26521 sets the jitter attenuator limit trip set (JALTS) bit in the LIU Latched Status register (LLSR.3).
In T1/J1 mode, the jitter attenuator corner frequency is 3.75Hz and in E1 mode it is 0.6Hz.
The DS26521 jitter attenuator is complaint with the following specifications shown in
Table 8-34. Jitter Attenuator Standards Compliance
Figure 8-21. Jitter Attenuation
ITU-T I.431, G.703, G.736, G.823
ETS 300 011, TBR 12/12
AT&T TR62411, TR43802
TR-TSY-009, TR-TSY-253, TR-TSY-499
-20dB
-40dB
-60dB
0dB
1
STANDARD
10
E1
Prohibited
TBR12
Area
T1
100
FREQUENCY (Hz)
76 of 258
P-P
1K
(buffer depth is 128 bits) or 28UI
Prohibited Area
ITU G.7XX
TR 62411 (Dec. 90)
Prohibited Area
10K
DS26521 Single T1/E1/J1 Transceiver
Figure
Table
100K
8-21. The jitter attenuator
8-34.
P-P
(buffer depth is