DS26521L+ Maxim Integrated Products, DS26521L+ Datasheet - Page 49

• Manufacturer Part Number: DS26521L+
• Description: IC TXRX T1/E1/J1 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26521L+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 220 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.9.5.2 Receive Bit-Oriented Code (BOC) Controller
The DS26521 framer contains a BOC generator on the transmit side and a BOC detector on the receive side. The
BOC function is available only in T1, ESF mode in the data link bits.
receive BOC operation.
Table 8-14. Registers Related to T1 Receive BOC
Receive BOC Control Register
(T1RBOCC)
Receive BOC Register (T1RBOC)
Receive Latched Status Register 7(RLS7)
Receive Interrupt Mask Register 7 (RIM7)
In ESF mode, the DS26521 continuously monitors the receive message bits for a valid BOC message. The BOC
detect (BD) status bit at RLS7.0 is set once a valid message has been detected for a time determined by the
receive BOC filter bits RBF0 and RBF1 in the
T1RBOC
BOC is detected following a BOC clear event). The BOC clear (BC) bit at RLS7.1 is set when a valid BOC is no
longer being detected for a time determined by the receive BOC disintegration bits RBD0 and RBD1 in the
T1RBOCC
The BD and BC status bits can create a hardware interrupt on the INTB signal as enabled by the associated
interrupt mask bits in the
8.9.5.3 Legacy T1 Transmit FDL
It is recommended that the DS26521’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL.
Table 8-15. Registers Related to T1 Transmit FDL
Transmit FDL Register (T1TFDL)
Transmit Control Register 2 (TCR2)
Transmit Latched Status Register 2 (TLS2)
Transmit Interrupt Mask Register 2 (HDLC)
(TIM2)
When enabled with TCR2.7, the transmit section shifts out into the T1 data stream either the FDL (in the ESF
framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (T1TFDL). When a
new value is written to the T1TFDL, it is multiplexed serially (LSB first) into the proper position in the outgoing T1
data stream. After the full eight bits have been shifted out, the framer signals the host controller that the buffer is
empty and that more data is needed by setting the TLS2.4 bit to a 1. The INTB bit also toggles low if enabled via
TIM2.4. The user has 2ms to update the
the
strongly suggested that the HDLC controller be used for FDL messaging applications.
In the D4 framing mode, the framer uses the
the
register).
T1TFDL
T1TFDL
register. Once the user has cleared the BD bit, it remains clear until a new BOC is detected (or the same
register.
register must be programmed to 1Ch and TCR2.7 should be set to 0 (source Fs data from the
is transmitted once again. Note that in this mode, no zero stuffing is applied to the FDL data. It is
REGISTER
REGISTER
Table 8-16
RIM7
shows the registers related to control of the transmit FDL.
register.
T1TFDL
T1TFDL
ADDRESSES
T1RBOCC
FRAMER
ADDRESSES
with a new value. If the
015h
063h
096h
0A6h
FRAMER
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register to insert the Fs framing pattern. To accomplish this,
1A1h
162h
182h
191h
register. The 6-bit BOC message is available in the
Controls the receive BOC function.
Receive bit-oriented message.
Indicates changes to the receive bit-oriented
messages.
Mask bits for RBOC for generation of
interrupts.
Table 8-14
FDL code used to insert transmit FDL.
Defines the source of the FDL.
Transmit FDL empty bit.
Mask bit for TFDL empty.
T1TFDL
DS26521 Single T1/E1/J1 Transceiver
shows the registers related to the
FUNCTION
is not updated, the old value in
FUNCTION
T1TFDL