DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 54
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DSPIC30F5015-30I/PT
Manufacturer Part Number
DSPIC30F5015-30I/PT
Description
DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F5015-30IPT.pdf
(230 pages)
Specifications of DSPIC30F5015-30I/PT
A/d Inputs
16-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
52
Interface
CAN, I2C, SPI, UART/USART
Ios
52
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
66K Bytes
Ram Size
2K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Company:
Part Number:
DSPIC30F5015-30I/PT
Manufacturer:
Microchip Technology
Quantity:
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dsPIC30F5015/5016
6.6.3
Example 6-2 shows a sequence of instructions that
can be used to load the 96 bytes of write latches.
32 TBLWTL and 32 TBLWTH instructions are needed to
load the write latches selected by the Table Pointer.
EXAMPLE 6-2:
6.6.4
For protection, the write initiate sequence for NVMKEY
must be used to allow any erase or program operation
to proceed. After the programming command has been
executed, the user must wait for the programming time
until programming is complete. The two instructions
following the start of the programming sequence
should be NOPs.
EXAMPLE 6-3:
DS70149C-page 52
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
; Perform the TBLWT instructions to write the latches
; 0th_program_word
; 1st_program_word
;
; 31st_program_word
Note: In Example 6-2, the contents of the upper byte of W3 has no effect.
2nd_program_word
MOV
MOV
MOV
MOV
MOV
TBLWTL W2
TBLWTH W3
MOV
MOV
TBLWTL W2
TBLWTH W3
MOV
MOV
TBLWTL W2
TBLWTH W3
•
•
•
MOV
MOV
TBLWTL W2
TBLWTH W3
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
LOADING WRITE LATCHES
INITIATING THE PROGRAMMING
SEQUENCE
#0x0000,W0
W0
#0x6000,W0
#LOW_WORD_0,W2
#HIGH_BYTE_0,W3
#LOW_WORD_1,W2
#HIGH_BYTE_1,W3
#LOW_WORD_2,W2
#HIGH_BYTE_2,W3
#LOW_WORD_31,W2
#HIGH_BYTE_31,W3
#5
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
,
,
,
,
,
,
,
,
,
,
,
LOADING WRITE LATCHES
INITIATING A PROGRAMMING SEQUENCE
TBLPAG
[W0]
[W0++]
[W0]
[W0++]
NVMKEY
NVMKEY
[W0]
[W0++]
[W0]
[W0++]
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 0x55 key
;
; Write the 0xAA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
;
; Initialize PM Page Boundary SFR
; An example program memory address
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
© 2007 Microchip Technology Inc.
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