DS2154L+ Maxim Integrated Products, DS2154L+ Datasheet - Page 7

• Manufacturer Part Number: DS2154L+
• Description: IC TXRX E1 1CHIP 5V ENH 100-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2154L+

• Number Of Drivers/receivers: 1/1
• Protocol: E1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 1.544 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2 Functional Description
The analog AMI/HDB3 waveform off the E1 line is transformer-coupled into the RRING and RTIP pins
of the DS2154. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS2154 contains an active filter that reconstructs the analog received
signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of
0dB to -43dB, which allows the device to operate on cables over 2km in length. The receive side framer
locates the FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms,
including carrier loss, loss of synchronization, AIS, and remote alarm. If needed, the receive side elastic
store can be enabled in order to absorb the phase and frequency differences between the recovered E1
data stream and an asynchronous backplane clock that is provided at the RSYSCLK input. The clock
applied at the RSYSCLK input can be either a 2.048MHz clock or a 1.544MHz clock. The RSYSCLK
can be a bursty clock with speeds up to 8.192MHz.
The transmit side of the DS2154 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter
attenuation mux to the waveshaping and line driver functions. The DS2154 will drive the E1 line from the
TTIP and TRING pins via a coupling transformer. The line driver contains a current limiter that restricts
the maximum current into a 1Ω load to less than 50mA (RMS).
1.3 Reader’s Note
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
time slots in an E1 system numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32
time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to
channel 1, time slot 1 is identical to Channel 2, and so on. Each time slot (or channel) is made up of 8 bits
numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is
transmitted last. Throughout this data sheet, the following abbreviations are used:
FAS
CRC4
CCS
CAS
MF
Sa
Si
E-Bit
Frame Alignment Signal
Cyclical Redundancy Check
Common Channel Signaling
Channel Associated Signaling
Multiframe
Additional Bits
International Bits
CRC4 Error Bits
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