DS21348G+ Maxim Integrated Products, DS21348G+ Datasheet - Page 16

• Manufacturer Part Number: DS21348G+
• Description: IC LIU T1/E1/J1 3.3V 49-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS21348G+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 49-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name,
DS21348T Pin Numbering)
WR (R/W)
BIS0/BIS1
BPCLK
NAME
TRING
NAME
MCLK
HRST
OCES
PBEO
TTIP/
VDD
VSM
ICES
VSS
INT
NA
CS
34/37
21/36
22/35
32/33
PIN
PIN
20
31
29
23
30
—
24
3
1
8
9
I/O
I/O
—
—
O
O
O
O
I
I
I
I
I
I
I
I
I
Transmit Tip and Ring [TTIP AND TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line. See
Section
Positive Supply. 3.3V ±5%
Voltage Supply Mode. Should be low for 3.3V operation.
Signal Ground
Write Input (Read/Write), Active Low. See the bus timing
diagrams in Section 11.
Bus Interface Select Bits 0 and 1. Used to select bus interface
option. See
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
Chip Select, Active Low. Active-low signal must be low to read or
write to the device.
Hardware Reset, Active Low. Bringing HRST low will reset the
DS21348 setting all control bits to their default state of all zeros.
Input Clock Edge Select. Selects whether the serial port data input
(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
Interrupt, Active Low. Flags host controller during conditions and
change of conditions defined in the Status Register. Active-low,
open-drain output.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
Not Assigned. Should be tied low.
Output Clock Edge Select. Selects whether the serial port data
output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PRBS Bit Error Output. The receiver will constantly search for a
2
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
15
-1 or a 2
5
for details.
20
Table 2-1
16 of 76
-1 PRBS depending on the ETS bit setting (CCR1.7).
for details.
FUNCTION
FUNCTION