PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 27
PIC18F1320-I/SO
Manufacturer Part Number
PIC18F1320-I/SO
Description
Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F1320-ISO.pdf
(310 pages)
Specifications of PIC18F1320-I/SO
A/d Inputs
7-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SOIC
Programmable Memory
8K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F1320-I/SO
Manufacturer:
MICROCHIP
Quantity:
35 000
Part Number:
PIC18F1320-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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3.3.3
In RC_IDLE mode, the CPU is disabled, but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.
If the IRCF bits are set to a non-zero value (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
INTOSC source stabilizes. If the IRCF bits were
previously at a non-zero value before the SLEEP
FIGURE 3-7:
FIGURE 3-8:
2004 Microchip Technology Inc.
Peripheral
Program
Counter
INTRC
OSC1
Clock
Clock
CPU
Note 1: T
CPU Clock
Multiplexer
PLL Clock
Peripheral
Program
INTOSC
Counter
Output
OSC1
Clock
Q1
RC_IDLE MODE
Q2
Wake from Interrupt Event
OST
PC
Q3
= 1024 T
Q4
PC
Q4
TIMING TRANSITION TO RC_IDLE MODE
TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q1
OSC
1
Q1
; T
T
OST
PLL
2
(1)
Q2
= 2 ms (approx). These intervals are not shown to scale.
PC + 2
3
OSTS bit Set
Clock Transition
T
PLL
Q3
4
(1)
5
Q4
PC + 2
6
Q1
1
2
7
instruction was executed and the INTOSC source was
already stable, the IOFS bit will remain set. If the IRCF
bits are all clear, the INTOSC output is not enabled and
the IOFS bit will remain clear; there will be no indication
of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a 10 s
delay following the wake event, the CPU begins exe-
cuting code, being clocked by the INTOSC multiplexer.
The microcontroller operates in RC_RUN mode until
the primary clock becomes ready. When the primary
clock becomes ready, a clock switchback to the primary
clock occurs (see Figure 3-8). When the clock switch is
complete, the IOFS bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock.
The IDLEN and SCS bits are not affected by the wake-
up. The INTRC source will continue to run if either the
WDT or the Fail-Safe Clock Monitor is enabled.
Clock Transition
3
8
4
PIC18F1220/1320
5
PC + 4
6
7
8
Q2
Q3 Q4
DS39605C-page 25
Q1
PC + 6
Q2
Q3
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