PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 106

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1320-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
12.1
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
FIGURE 12-1:
FIGURE 12-2:
DS39605C-page 104
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T13CKI/T1OSO
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates
T13CKI/T1OSO
Timer1 Operation
TMR1IF
Overflow
Interrupt
Flag bit
Data Bus<7:0>
Write TMR1L
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag bit
T1OSI
T1OSI
power drain.
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
8
T1OSC
High Byte
T1OSC
TMR1H
Timer 1
8
TMR1H
8
TMR1
TMR1
Oscillator
Enable
T1OSCEN
T1OSCEN
Enable
Oscillator
TMR1L
TMR1L
8
(1)
CLR
(1)
CLR
Clock
Internal
F
OSC
Clock
Internal
F
OSC
/4
TMR1ON
CCP Special Event Trigger
On/Off
/4
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/T1OSO/
T13CKI/P1C/KBI2 pins become inputs. That is, the
TRISB7:TRISB6 values are ignored and the pins read
as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
TMR1ON
TMR1CS
CCP Special Event Trigger
on/off
1
0
TMR1CS
1
0
T1CKPS1:T1CKPS0
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
T1SYNC
Prescaler
1, 2, 4, 8
0
1
2
0
1
2
 2004 Microchip Technology Inc.
Synchronized
Clock Input
Peripheral Clocks
Synchronized
Synchronize
Clock Input
Peripheral Clocks
Synchronize
det
det