PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 224

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PIC18F1320-I/SO

Manufacturer Part Number
PIC18F1320-I/SO
Description
Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F1320-I/SO

A/d Inputs
7-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SOIC
Programmable Memory
8K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F1320-I/SO
Manufacturer:
MICROCHIP
Quantity:
35 000
Part Number:
PIC18F1320-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F1220/1320
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39605C-page 222
Q Cycle Activity:
After Interrupt
operation
Decode
PC
W
BSR
Status
GIE/GIEH, PEIE/GIEL
Q1
No
operation
operation
Return from Interrupt
[ label ]
s
(TOS)
1
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged.
GIE/GIEH, PEIE/GIEL.
Return from interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
1
2
RETFIE
0000
Q2
No
No
[0,1]
GIE/GIEH or PEIE/GIEL,
W,
PC,
1
RETFIE [s]
0000
BSR,
=
=
=
=
=
operation
operation
Status,
Q3
No
No
TOS
WS
BSRS
STATUSS
1
0001
Set GIEH or
from stack
operation
Pop PC
GIEL
Q4
No
000s
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
TABLE
Q Cycle Activity:
:
:
:
CALL TABLE ; W contains table
ADDWF PCL
RETLW k0
RETLW k1
RETLW kn
Before Instruction
After Instruction
operation
Decode
W
W
Q1
No
; offset value
; W now has
; table value
; W = offset
; Begin table
;
; End of table
=
=
operation
Return Literal to W
[ label ]
0
k
(TOS)
PCLATU, PCLATH are unchanged
None
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
1
2
literal ‘k’
Read
0000
Q2
No
0x07
value of kn
k
 2004 Microchip Technology Inc.
W,
255
PC,
RETLW k
1100
operation
Process
Data
Q3
No
kkkk
from stack,
Write to W
operation
Pop PC
Q4
No
kkkk

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