PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet - Page 53

• Manufacturer Part Number: PIC24FJ64GA006-I/PT
• Description: 64 PIN, 64KB FLASH, 8 KB RAM, 53 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA006-I/PT

• A/d Inputs: 16 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 53
• Number Of Pins: 64
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 16 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Pin Reset
• SWR: RESET Instruction
• WDT: Watchdog Timer Reset
• BOR: Brown-out Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module is
shown in Figure 5-1.
Any active source of Reset will make the SYSRST sig-
nal active. Many registers associated with the CPU and
peripherals are forced to a known Reset state. Most
registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
FIGURE 5-1:
© 2006 Microchip Technology Inc.
RESETS
MCLR
V
DD
Enable Voltage Regulator
Uninitialized W Register
RESET SYSTEM BLOCK DIAGRAM
Instruction
RESET
Sleep or Idle
Illegal Opcode
Module
WDT
Brown-out
Trap Conflict
V
DD
Detect
Reset
Rise
Glitch Filter
POR
Preliminary
BOR
PIC24FJ128GA FAMILY
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 5-1). A POR will clear all bits except for
the BOR and POR bits (RCON<1:0>), which are set.
The user may set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software will
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
SYSRST
DS39747C-page 51