PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet
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... Microchip Technology Inc. PIC24FJ128GA Family General Purpose, 16-Bit Flash Microcontrollers Preliminary Data Sheet DS39747C ...
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... MCUs, K ® EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , microID, MPLAB, PIC, PICmicro, PICSTART code hopping devices, Serial ® © 2006 Microchip Technology Inc. ...
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... Oscillator Start-up Timer (OST) • Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for reliable operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 pins Program Device Pins Memory (Bytes) (Bytes) PIC24FJ64GA006 64 64K PIC24FJ96GA006 64 96K PIC24FJ128GA006 64 128K PIC24FJ64GA008 80 ...
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... MCLR PMA2/SS2/CN11/RG9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/V -/AN1/CN3/RB1 REF PGD1/EMUD1/PMA6/V +/AN0/CN2/RB0 REF DS39747C-page PIC24FJXXGA006 8 PIC24FJXXXGA006 Preliminary 48 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/RD0 45 IC4/PMCS1/INT4/RD11 44 IC3/PMCS2/INT3/RD10 43 IC2/U1CTS//INT2/RD9 42 IC1/RTCC/INT1/RD8 41 Vss 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/BCLK1/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 © 2006 Microchip Technology Inc. ...
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... T2CK/RC1 4 T4CK/RC3 5 PMA5/SCK2/CN8/RG6 6 PMA4/SDI2/CN9/RG7 7 PMA3/SDO2/CN10/RG8 8 MCLR 9 PMA2/SS2/CN11/RG9 TMS/INT1/RE8 13 TDO/INT2/RE9 14 C1IN+/AN5/CN7/RB5 15 C1IN-/AN4/CN6/RB4 16 C2IN+/AN3/CN5/RB3 17 C2IN-/AN2/SS1/CN4/RB2 18 PGC1/EMUC1/AN1/CN3/RB1 19 PGD1/EMUD1/AN0/CN2/RB0 20 © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY PIC24FJXXGA008 50 PIC24FJXXXGA008 Preliminary SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 SDA2/INT4/RA15 SCL2/INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 ...
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... C1IN-/AN4/CN6/RB4 21 C2IN+/AN3/CN5/RB3 22 C2IN-/AN2/SS1/CN4/RB2 23 PGC1/EMUC1/AN1/CN3/RB1 24 PGD1/EMUD1/AN0/CN2/RB0 25 DS39747C-page PIC24FJXXGA010 63 PIC24FJXXXGA010 Preliminary V SS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 V DD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2006 Microchip Technology Inc. ...
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... Electrical Characteristics .......................................................................................................................................................... 201 27.0 Packaging Information.............................................................................................................................................................. 213 Appendix A: Revision History............................................................................................................................................................. 219 Index ................................................................................................................................................................................................. 221 The Microchip Web Site ..................................................................................................................................................................... 225 Customer Change Notification Service .............................................................................................................................................. 225 Customer Support .............................................................................................................................................................................. 225 Reader Response .............................................................................................................................................................................. 226 Product Identification System ............................................................................................................................................................ 227 © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Preliminary DS39747C-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39747C-page 6 Preliminary © 2006 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC24FJ64GA006 • PIC24FJ64GA008 • PIC24FJ64GA010 • PIC24FJ96GA006 • PIC24FJ96GA008 • PIC24FJ96GA010 • PIC24FJ128GA006 • PIC24FJ128GA008 • PIC24FJ128GA010 This family introduces a new line of Microchip devices: a 16-bit RISC microcontroller family with a broad peripheral feature set and enhanced computational performance ...
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... C the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Preliminary memory (64 Kbytes for devices, 96 Kbytes for pin features available on the © 2006 Microchip Technology Inc. ...
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... SPI (3-wire/4-wire C™ Parallel Communications (PMP/PSP) JTAG Boundary Scan 10-bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and Delays) Instruction Set Packages © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY DC – 32 MHz 96K 128K 64K 96K 32,768 44,032 22,016 32,768 8192 43 (39/4) ...
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... Multiplier (2) MCLR 10-bit Timer4/5 RTCC ADC (1) CN1-22 SPI1/2 I2C1/2 Preliminary (1) PORTA RA0:RA7, 16 RA9:RA10, RA14:15 PORTB RB0:RB15 (1) PORTC RC1:RC4, RC12:RC15 (1) PORTD 16 RD0:RD15 (1) PORTE RE0:RE9 (1) PORTF RF0:RF8, RF12:RF13 16-bit ALU 16 (1) PORTG RG0:RG9, RG12:RG15 Comparators PMP/PSP UART1/2 © 2006 Microchip Technology Inc. ...
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... CN13 52 66 CN14 53 67 CN15 54 68 CN16 55 69 CN17 31 39 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Input I/O Buffer 100-pin 25 I ANA A/D Analog Inputs ANA 23 I ANA 22 I ANA 21 ...
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... In-Circuit Debugger and ICSP™ Programming Clock 25 I/O ST In-Circuit Debugger and ICSP Programming Data. 26 I/O ST In-Circuit Debugger and ICSP™ Programming Clock. 27 I/O ST In-Circuit Debugger and ICSP Programming Data Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2006 Microchip Technology Inc. ...
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... PMD7 3 3 PMRD 53 67 PMWR 52 66 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Input I/O Buffer 100-pin 44 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). 43 I/O ...
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... I/O ST PORTB Digital I/ I/O ST PORTC Digital I/ Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2006 Microchip Technology Inc. ...
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... RF5 32 40 RF6 35 45 RF7 — 44 RF8 — 43 RF12 — — RF13 — — Legend: TTL = TTL input buffer ANA = Analog level input/output © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Input I/O Buffer 100-pin 72 I/O ST PORTD Digital I/ I/O ...
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... Timer4 External Clock Input Timer5 External Clock Input JTAG Test Clock/Programming Clock Input JTAG Test Data/Programming Data Input — JTAG Test Data Output JTAG Test Mode Select Input Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2006 Microchip Technology Inc. ...
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... DDCORE REF REF V 9, 25, 41 11, 31, 51 15, 36, 45, SS Legend: TTL = TTL input buffer ANA = Analog level input/output © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Input I/O Buffer 100-pin UART1 Clear to Send Input — UART1 Request to Send Output UART1 Receive DIG UART1 Transmit Output ...
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... PIC24FJ128GA FAMILY NOTES: DS39747C-page 18 Preliminary © 2006 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... Various Blocks DS39747C-page 20 Data Bus 16 16 Data Latch PCH PCL Data RAM Address Loop Latch Control Logic RAGU WAGU EA MUX ROM Latch 16 Instruction Reg Hardware Multiplier Register Array Divide Support Preliminary 16-Bit ALU 16 To Peripheral Modules © 2006 Microchip Technology Inc. ...
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... W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Description Working register array 23-bit Program Counter ALU STATUS register Stack Pointer Limit Value register Table Memory Page Address register ...
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... R/W-0 R-0 R/W-0 (2) (2) IPL0 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U -0 R/W-0 — DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — ...
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... All multi-bit shift instructions only support register direct addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. Description Preliminary © 2006 Microchip Technology Inc. ...
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... Registers Reserved DEVID (2) Note: Memory areas are not shown to scale. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 “Interfacing Program and Data Memory Spaces”. ...
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... PIC24FJ128GA least significant word Instruction Width Preliminary Words are provided in FLASH CONFIGURATION WORDS FOR PIC24FJ128GA FAMILY DEVICES Program Configuration Memory Word (K words) Addresses 22 00ABFCh: 00ABFEh 32 00FFFCh: 00FFFEh 44 0157FCh: 0157FEh PC Address (lsw Address) 0 000000h 000002h 000004h 000006h © 2006 Microchip Technology Inc. ...
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... FFFFh Note: Data memory areas are not shown to scale. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY PIC24FJ128GA family devices implement a total of 8 Kbytes of data memory. Should an EA point to a loca- tion outside of this area, an all zero word or byte will be returned ...
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... CRC — — System NVM/PMD — Preliminary xxA0 xxC0 xxE0 Interrupts — — — — — I/O — I/O — — — — — — — I/O — — — © 2006 Microchip Technology Inc. ...
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TABLE 3-3: CPU CORE REGISTERS MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
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TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...
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TABLE 3-5: ICN REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — — — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CNPU2 006A — ...
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TABLE 3-7: INPUT CAPTURE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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TABLE 3-9: I2C1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL ...
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TABLE 3-11: UART1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — — ...
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TABLE 3-15: ADC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
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TABLE 3-17: PORTB REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 PORTB 02C8 RB15 RB14 RB13 RB12 LATB 02CA LATB15 LATB14 LATB13 LATB12 ODCB 06C6 ODB15 ODB14 ODB13 ODB12 ...
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TABLE 3-20: PORTE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISE 02D8 — — — — PORTE 02DA — — — — LATE 02DC — — — — ODCE 06D8 — — — — ...
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TABLE 3-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 (1) PMADDR CS2 CS1 0604 (1) ...
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TABLE 3-27: CRC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CRCCON 0640 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCXOR 0642 CRCDAT 0644 CRCWDAT 0646 Legend: — = unimplemented, read as ...
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... Table 3-31 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. Preliminary © 2006 Microchip Technology Inc. ...
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... Note 1: The LSb of program space addresses is always fixed as ‘0’, in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Program Space Address <23> ...
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... TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 800000h Only read operations are shown; write operations are also valid in the user memory area. Preliminary Data EA<15:0> © 2006 Microchip Technology Inc. ...
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... PSVPAG is mapped into the upper half of the data memory space.... © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
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... PIC24FJ128GA FAMILY NOTES: DS39747C-page 44 Preliminary © 2006 Microchip Technology Inc. ...
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... Using Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- tions (192 bytes time, and erase program memory in blocks of 512 instructions (1536 bytes time ...
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... Flash in RTSP mode. A programming operation is nominally duration and the processor stalls (waits) until the oper- ation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. Preliminary © 2006 Microchip Technology Inc. ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP3:NVMOP0 are unimplemented. Legend Readable bit W = Writable bit -n = Value at Reset ‘1’ = Bit is set © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — ...
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... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2006 Microchip Technology Inc. ...
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... MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ...
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... PIC24FJ128GA FAMILY NOTES: DS39747C-page 50 Preliminary © 2006 Microchip Technology Inc. ...
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... DD Brown-out Reset Enable Voltage Regulator Trap Conflict Illegal Opcode Uninitialized W Register © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A POR will clear all bits except for the BOR and POR bits (RCON< ...
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... CM R/W-0 R/W-0 R/W-0 SWDTEN WDTO SLEEP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 VREGS bit 8 R/W-0 R/W-1 R/W-1 IDLE BOR POR bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... SWITCHING ENABLED) Reset Type Clock Source Determinant POR Oscillator Configuration Bits (FNOSC2:FNOSC0) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTR SWR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Setting Event POR POR POR POR PWRSAV instruction, POR POR POR — — 5.2 ...
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... FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. Preliminary FSCM Notes Delay — FSCM FSCM FSCM — FSCM FSCM FSCM — 3 — 3 — 3 — 3 — 3 — 3 (64 ms nominal) if on-chip © 2006 Microchip Technology Inc. ...
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... PLL to stabilize. In most cases, the FSCM delay will prevent an oscillator failure trap at a device Reset when the PWRT is disabled. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 5.3 Special Function Register Reset ...
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... PIC24FJ128GA FAMILY NOTES: DS39747C-page 56 Preliminary © 2006 Microchip Technology Inc. ...
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... PIC24FJ128GA family devices implement maskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT as shown in Figure 6-1. Access to the ...
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... Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h — — — 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 0001172h Reserved Preliminary (1) (1) Trap Source © 2006 Microchip Technology Inc. ...
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... SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Vector AIVT IVT Address Number Address 13 00002Eh 00012Eh 18 000038h 000138h 67 00009Ah ...
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... IPL2:IPL0, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All interrupt registers are described in Register 6-1 through Register 6-30, in the following pages. Preliminary © 2006 Microchip Technology Inc. ...
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... CPU interrupt priority level is greater than 7; peripheral interrupts are disabled 0 = CPU interrupt priority level less Note 1: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — ...
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... U-0 R/W-0 R/W-0 — MATHERR ADDRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 — — bit 8 R/W-0 R/W-0 U-0 STKERR OSCFAIL — bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — — U-0 ...
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... SPF1IF R/W-0 U-0 R/W-0 IC2IF — T1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 T3IF bit 8 R/W-0 R/W-0 R/W-0 OC1IF IC1IF INT0IF bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF ...
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... OC5IF R/W-0 U-0 U-0 IC3IF — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 — bit 8 U-0 R/W-0 R/W-0 — SPI2IF SPF2IF bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — — ...
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... U-0 U-0 R/W-0 — — CRCIF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 — — bit 8 R/W-0 R/W-0 U-0 U2ERIF U1ERIF — bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE SPF1IE R/W-0 U-0 ...
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... OC4IE OC3IE U-0 R/W-0 R/W-0 — INT1IE CNIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 — bit 8 R/W-0 R/W-0 R/W-0 CMIE MI2C1IE SI2C1IE bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 R/W-0 — — — OC5IE ...
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... R/W-0 U-0 U-0 INT3IE — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 — — bit 8 R/W-0 R/W-0 U-0 MI2C2IE SI2C2IE — bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — — U-0 ...
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... OC1IP2 OC1IP1 R/W-0 R/W-0 U-0 IC1IP1 IC1IP0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 OC1IP0 bit 8 R/W-1 R/W-0 R/W-0 INT0IP2 INT0IP1 INT0IP0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 U-0 R/W-1 R/W-0 T2IP0 — OC2IP2 OC2IP1 R/W-0 R/W-0 ...
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... R/W-0 R/W-0 U-0 SPF1IP1 SPF1IP0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP1 SPI1IP0 bit 8 R/W-1 R/W-0 R/W-0 T3IP2 T3IP1 T3IP0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — — R/W-0 R/W-0 ...
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... CMIP2 CMIP1 R/W-0 R/W-0 U-0 MI2C1P1 MI2C1P0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 CMIP0 bit 8 R/W-1 R/W-0 R/W-0 SI2C1P2 SI2C1P1 SI2C1P0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... OC4IP2 OC4IP1 R/W-0 R/W-0 U-0 OC3IP1 OC3IP0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 OC4IP0 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 83
... T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 U2RXIP1 R/W-0 R/W-0 ...
Page 84
... R/W-0 R/W-0 U-0 SPI2IP1 SPI2IP0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 — — bit 8 R/W-1 R/W-0 R/W-0 SPF2IP2 SPF2IP1 SPF2IP0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 85
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 U-0 R/W-1 R/W-0 IC5IP0 — IC4IP2 IC4IP1 R/W-0 R/W-0 ...
Page 86
... U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 — — bit 8 U-0 U-0 U-0 — — — bit Bit is unknown U-0 — — bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 87
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 R/W-1 R/W-0 — — MI2C2P2 MI2C2P1 R/W-0 R/W-0 ...
Page 88
... INT4IP2 INT4IP1 R/W-0 R/W-0 U-0 INT3IP1 INT3IP0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 INT4IP0 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 89
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ . Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 R/W-1 R/W-0 — — RTCIP2 RTCIP1 U-0 U-0 U-0 — ...
Page 90
... U2ERIP1 R/W-0 R/W-0 U-0 U1ERIP1 U1ERIP0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2ERIP0 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 91
... ISR will be re-entered immediately after exiting the rou- tine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 92
... PIC24FJ128GA FAMILY NOTES: DS39747C-page 90 Preliminary © 2006 Microchip Technology Inc. ...
Page 93
... Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY • On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources • Software-controllable switching between various clock sources • ...
Page 94
... FRC oscillator over a range of approximately ±12%. Each bit increment or decrement changes the factory calibrated frequency of the FRC oscillator by a fixed amount. Preliminary FNOSC2: Note FNOSC0 1, 2 111 1 110 1 101 1 100 011 011 011 010 010 010 1 001 1 000 © 2006 Microchip Technology Inc. ...
Page 95
... Note 1: Reset values for these bits are determined by the FNOSC Configuration bits. 2: Also resets to ‘0’ during any valid clock switch, or whenever a non-PLL Clock mode is selected. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY (1) R-0 U-0 R/W-x ...
Page 96
... RCDIV2 RCDIV1 U-0 U-0 U-0 — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 RCDIV0 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 97
... HS and EC) which are determined by the POSCMD Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — ...
Page 98
... MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV.b #0x01, w0 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation MOV.b w0, [w1] Preliminary in two back-to-back 46h and 57h to © 2006 Microchip Technology Inc. ...
Page 99
... PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Note: SLEEP_MODE and IDLE_MODE are con- stants defined in the assembler include file for the selected device. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset ...
Page 100
... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows fur- ther reduction of power consumption during Idle mode, possible enhancing power savings for extremely critical power applications. Preliminary © 2006 Microchip Technology Inc. ...
Page 101
... CK WR Port Data Latch Read LAT Read Port © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 102
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. Preliminary © 2006 Microchip Technology Inc. ...
Page 103
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...
Page 104
... R/W-0 R/W-0 U-0 TCKPS1 TCKPS0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 105
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> ...
Page 106
... T2CON and T4CON registers. * The ADC Event Trigger is available only on Timer4/5. DS39747C-page 104 1x Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR3 TMR2 (TMR5) (TMR4 TMR3HLD 16 (TMR5HLD) Preliminary TCKPS1:TCKPS0 TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2006 Microchip Technology Inc. ...
Page 107
... Reset Equal FIGURE 11-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) TGATE 1 Set T3IF (T5IF) 0 Reset ADC Event Trigger* Equal * The ADC Event Trigger is available only on Timer4/5. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 1x Gate Sync TMR2 (TMR4) Sync ...
Page 108
... R/W-0 R/W-0 R/W-0 TCKPS1 TCKPS0 T32 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 109
... Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 — — ...
Page 110
... PIC24FJ128GA FAMILY NOTES: DS39747C-page 108 Preliminary © 2006 Microchip Technology Inc. ...
Page 111
... ICx pin ICM<2:0>(ICxCON<2:0>) 3 Mode Select ICOV, ICBNE(ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Edge Detection Logic FIFO R/W and Clock Synchronizer Logic ICI<1:0> ...
Page 112
... ICOV ICBNE U = Unimplemented bit, read as ‘0’ Writable bit HS = Set in Hardware ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 R/W-0 ICM2 ICM1 ICM0 bit Cleared in Hardware x = Bit is unknown © 2006 Microchip Technology Inc. ...
Page 113
... TMRy register are not required, but may be advantageous for defining a pulse from a known event time boundary. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY The output compare module does not have to be dis- abled after the falling edge of the output pulse. Another pulse can be initiated by rewriting the value of the OCxCON register ...
Page 114
... Table 13-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F • (Timer Prescale Value) PWM log ( /2, Doze mode and PLL are disabled. CY OSC Preliminary CALCULATING THE PWM (1) PERIOD • (Timer Prescale Value /2, Doze mode and CY OSC (1) ) bits © 2006 Microchip Technology Inc. ...
Page 115
... OCFA pin controls OC1-OC4 channels. OCFB pin controls OC5-OC8 channels. 3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time bases associated with the module. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY • (Timer 2 Prescale Value) ...
Page 116
... OCFLT OCTSEL U = Unimplemented bit, read as ‘0’ Writable bit HS = Set in Hardware ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 R/W-0 OCM2 OCM1 OCM0 bit Cleared in Hardware x = Bit is unknown © 2006 Microchip Technology Inc. ...
Page 117
... SPIx or separately as SPI1 and SPI2. Special Function Reg- isters will follow a similar notation. For example, SPIxCON refers to the control register for the SPI1 or SPI2 module. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY To set up the SPI module for the Standard Master mode of operation: 1. ...
Page 118
... SPIBEN bit (SPIxCON2<0>). 8. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer (1) Write SPIxBUF 16 Internal Data Bus Preliminary registers with MSTEN 1:1/4/16/64 F Primary CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2006 Microchip Technology Inc. ...
Page 119
... Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 R-0 — ...
Page 120
... R/W-0 R/W-0 R/W-0 MSTEN SPRE2 SPRE1 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SMP CKE bit 8 R/W-0 R/W-0 R/W-0 SPRE0 PPRE1 PPRE0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 121
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (legacy mode) Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — — ...
Page 122
... SDOx Serial Clock SCKx SCKx SSx SSx SSEN (SPIxCON1<7> and MSTEN (SPIxCON1<5> and Preliminary (SPIxRXB) Shift Register (SPIxSR) LSb (SPIxTXB) SPIx Buffer (SPIxBUF) Shift Register (SPIxSR) MSb LSb 8-level FIFO Buffer SPIx Buffer (SPIxBUF) SPIBEN (SPIxCON2<0> © 2006 Microchip Technology Inc. ...
Page 123
... FIGURE 14-6: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24 (SPI Slave, Frame Slave) FIGURE 14-7: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24 (SPI Master, Frame Slave) © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx ...
Page 124
... Preliminary (1) 4:1 6:1 8:1 4000 2667 2000 1000 667 500 250 167 125 1250 833 625 313 208 156 © 2006 Microchip Technology Inc. ...
Page 125
... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 15-1. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 15.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 126
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2006 Microchip Technology Inc. ...
Page 127
... MHz is the minimum input clock frequency to have I2CxBRG cannot have a value of less than 2. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 15.3 Slave Address Masking The I2CxMSK register (Register 15-3) designates address bit positions as “don’t care” for both 7-bit and 10-bit Address modes ...
Page 128
... ACKDT ACKEN RCEN 2 C pins are controlled by port functions Slave slave Unimplemented bit, read as ‘0’ Set in Hardware ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 DISSLW SMEN bit 8 PEN RSEN SEN bit Cleared in Hardware x = Bit is unknown © 2006 Microchip Technology Inc. ...
Page 129
... Initiate Start condition on SDA and SCL pins Hardware clear at end of master Start sequence Start condition not in progress . Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M R/W-0 ...
Page 130
... R/C-0 HSC R/C-0 HSC D module is busy U = Unimplemented bit, read as ‘0’ Set in Hardware ‘0’ = Bit is cleared Preliminary R-0 HSC ADD10 bit 8 R-0 HSC R-0 HSC R-0 HSC R/W RBF TBF bit 0 HSC = Hardware Set/Cleared x = Bit is unknown © 2006 Microchip Technology Inc. ...
Page 131
... Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. . Legend Readable bit C = Clearable bit -n = Value at POR ‘1’ = Bit is set © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 R/C-0 HS R-0 HSC — — BCL ...
Page 132
... AMSK9 R/W-0 R/W-0 R/W-0 AMSK5 AMSK4 AMSK3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 AMSK8 bit 8 R/W-0 R/W-0 R/W-0 AMSK2 AMSK1 AMSK0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 133
... FIGURE 16-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UARTx Receiver UARTx Transmitter © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY • Fully Integrated Baud Rate Generator with 16-bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • ...
Page 134
... Preliminary /(16 * 65536). UART BAUD RATE WITH (1,2) BRGH = • (BRGx + – • Baud Rate denotes the instruction cycle clock = F /2, Doze mode CY OSC /4 CY (1) © 2006 Microchip Technology Inc. ...
Page 135
... Write ‘55h’ to TXxREG – loads Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 16.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
Page 136
... RXINV BRGH U = Unimplemented bit, read as ‘0’ Writable bit HC = Hardware Cleared ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary (1) (1) R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 R/W-0 PDSEL1 PDSEL0 STSEL bit Hardware Set x = Bit is unknown © 2006 Microchip Technology Inc. ...
Page 137
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Legend Readable bit -n = Value at Reset © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 R/W-0 U-0 R/W-0 IREN RTSMD — R/W-0 HC ...
Page 138
... ADDEN RIDLE PERR ( Unimplemented bit, read as ‘0’ Writable bit HS = Hardware Set ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-1 TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Hardware Cleared x = Bit is unknown © 2006 Microchip Technology Inc. ...
Page 139
... RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (Read-Only Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Legend Readable bit -n = Value at Reset © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 R/W-0 HC R/W-0 — UTXBRK UTXEN ...
Page 140
... PIC24FJ128GA FAMILY NOTES: DS39747C-page 138 Preliminary © 2006 Microchip Technology Inc. ...
Page 141
... PMP is highly configurable. FIGURE 17-1: PMP MODULE OVERVIEW PIC24F Parallel Master Port © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Key features of the PMP module include: • Programmable Address Lines • Two Chip Select Lines • Programmable Strobe Options - Individual Read and Write Strobes or ...
Page 142
... R/W-0 R/W-0 R/W-0 ALP CS2P CS1P ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 PTRDEN bit 8 R/W-0 R/W-0 R/W-0 BEP WRSP RDSP bit bit is unknown © 2006 Microchip Technology Inc. ...
Page 143
... For Master mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. Legend Readable bit -n = Value at Reset © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 R/W-0 R/W-0 ADRMUX1 ADRMUX0 PTBEEN ...
Page 144
... R/W-0 R/W-0 (1) WAITM3 WAITM2 WAITM1 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 MODE0 bit 8 R/W-0 R/W-0 R/W-0 (1) (1) WAITM0 WAITE1 WAITE0 bit 0 (1) ( Bit is unknown © 2006 Microchip Technology Inc. ...
Page 145
... PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O Legend Readable bit -n = Value at Reset © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 R/W-0 R/W-0 ADDR<13:8> R/W-0 R/W-0 R/W-0 ADDR< ...
Page 146
... R-0 R-0 — IB3F IB2F IB1F U-0 U-0 R-1 — — OB3E HC = Hardware Cleared U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-0 IB0F bit 8 R-1 R-1 R-1 OB2E OB1E OB0E bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 147
... PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers Legend Readable bit W = Writable bit -n = Value at Reset ‘1’ = Bit is set © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — ...
Page 148
... PMDOUT1<15:8> (1) PMDOUT2<7:0> (2) PMDOUT2<15:8> (3) PMA<13:0> PMD<7:0> PMCS1 PMCS2 PMRD PMWR Preliminary Address Bus Data Bus Control Lines Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) Input Register (Buffer) PMDIN1<7:0> (0) PMDIN1<15:8> (1) PMDIN2<7:0> (2) PMDIN2<15:8> (3) Address Bus Data Bus Control Lines © 2006 Microchip Technology Inc. ...
Page 149
... PMD<7:0> PMALL PMALH PMCS PMRD PMWR FIGURE 17-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMA<14:7> PMCS PMRD PMWR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 PMCS2 PMALL PMRD PMWR PMD<7:0> PMA<13:8> PMCS1 PMCS2 PMALL ...
Page 150
... Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> LCD Controller D<7:0> RS R/W E Preliminary Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines © 2006 Microchip Technology Inc. ...
Page 151
... RTCC Clock Domain 32.768 kHz Input from SOSC Oscillator RTCC Prescalers RTCC Timer Alarm Event Comparator Compare Registers with Masks Repeat Counter © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY CPU Clock Domain RCFGCAL ALCFGRPT 0.5s RTCVAL ALRMVAL RTCC Interrupt Logic Preliminary YEAR ...
Page 152
... Note: This only applies to read operations and YEAR not write operations. Preliminary uses the ALRMPTR bits will be accessible through ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMSEC ALRMWD ALRMHR ALRMMNTH ALRMDAY — — © 2006 Microchip Technology Inc. ...
Page 153
... RTCC output enabled 0 = RTCC output disabled Note 1: The RCFGCAL register is only affected by a POR write to the RTCEN bit is only allowed when RTCWREN = 1. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R-0 R-0 R/W-0 RTCOE RTCPTR1 RTCPTR0 R/W-0 ...
Page 154
... RTCPTR1 RTCPTR0 R/W-0 R/W-0 R/W-0 CAL5 CAL4 CAL3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 CAL2 CAL1 CAL0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 155
... PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers Legend Readable bit W = Writable bit -n = Value at Reset ‘1’ = Bit is set © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 U-0 — — ...
Page 156
... AMASK0 ALRMPTR1 ALRMPTR0 R/W-0 R/W-0 R/W-0 ARPT5 ARPT4 ARPT3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 ARPT2 ARPT1 ARPT0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 157
... DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from bit 3-0 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from Note 1: A write to this register is only allowed when RTCWREN = 1. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY (1) U-0 U-0 U-0 — ...
Page 158
... U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary (1) R/W-x R/W-x WDAY1 WDAY0 bit 8 R/W-x R/W-x R/W-x HRONE2 HRONE1 HRONE0 bit Bit is unknown R/W-x R/W-x bit 8 R/W-x R/W-x R/W-x bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 159
... HRONE3:HRONE0: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from Note 1: A write to this register is only allowed when RTCWREN = 1. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-x R/W-x R/W-x MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 ...
Page 160
... Note the user to include in the error value the initial error of the crystal, drift due to temperature and drift due to crystal aging. Preliminary R/W-x R/W-x MINONE1 MINONE0 bit 8 R/W-x R/W-x R/W-x bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 161
... Every year Note 1: Annually, except when configured for February 29. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY After each alarm is issued, the ALCFGRPT register is decremented by one. Once the register has reached ‘00’, the alarm will be issued one last time, after which the ALRMEN bit will be cleared automatically and the alarm will turn off ...
Page 162
... PIC24FJ128GA FAMILY NOTES: DS39747C-page 160 Preliminary © 2006 Microchip Technology Inc. ...
Page 163
... CRC serial shifter turned off bit 3-0 PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 19.1 Registers There are four registers used to control programmable CRC operation: • CRCCON • ...
Page 164
... The topology of a standard CRC generator is shown in Figure 19- CRC Shift Register Hold Hold X2 0 OUT OUT IN IN BIT 1 BIT 2 1 p_clk p_clk CRC Write Bus Preliminary EXAMPLE CRC SETUP Bit Value 1111 000100000010000 15 Hold X3 X15 0 0 OUT IN BIT p_clk CRC Read Bus © 2006 Microchip Technology Inc. ...
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... Once that is done, start the CRC by setting the CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY ...
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... PIC24FJ128GA FAMILY NOTES: DS39747C-page 164 Preliminary © 2006 Microchip Technology Inc. ...
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... Refer to the device data sheet for further details. A block diagram of the A/D converter is shown in Figure 20-1. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY To perform an A/D conversion: 1. Configure the A/D module: ...
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... S/H DAC V INL 10-Bit SAR Data Formatting ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 INH AD1CHS AD1PCFG AD1CSSL INL Sample Control Control Logic Input MUX Control Pin Config. Control Preliminary Internal Data Bus 16 Comparator + R Conversion Logic Conversion Control © 2006 Microchip Technology Inc. ...
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... A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-0 U-0 U-0 — — — R/W-0 ...
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... External V REF Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 R/W-0 SMPI0 BUFM ALTS bit pin REF - pin REF Bit is unknown © 2006 Microchip Technology Inc. ...
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... ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 128 • ······ 00000001 = T CY 00000000 = Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 SAMC1 R/W-0 R/W-0 R/W-0 ADCS5 ...
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... CH0SB1 U-0 U-0 R/W-0 — — CH0SA3 - Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CH0SB0 bit 8 R/W-0 R/W-0 R/W-0 CH0SA2 CH0SA1 CH0SA0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan Legend Readable bit -n = Value at POR EQUATION 20-1: A/D CONVERSION CLOCK PERIOD Note 1: Based on T © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/W-0 R/W-0 R/W-0 PCFG12 PCFG11 PCFG10 R/W-0 ...
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... Threshold Voltage Leakage Current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch Resistance Sample/Hold Capacitance (from DAC) HOLD Preliminary ≤ 5 kΩ (Typical HOLD = DAC capacitance = 4.4 pF (Typical negligible if Rs ≤ 5 kΩ. PIN © 2006 Microchip Technology Inc. ...
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... PIC24FJ devices not intended comprehensive reference source. FIGURE 21-1: COMPARATOR I/O OPERATING MODES C1NEG C1IN+ V C1IN- C1POS C1IN REF C2NEG C2IN+ V C2IN- C2POS C2IN REF © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY C1EN C1INV - C2EN C2INV - Preliminary CMCON<6> C1OUT C1OUTEN CMCON<7> C2OUT C2OUTEN ...
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... C2OUTEN C1OUTEN R/W-0 R/W-0 R/W-0 C2INV C1INV C2NEG W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 C2POS C1NEG C1POS bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... See Figure 21-1 for the comparator modes. bit 0 C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected Input is connected to CV See Figure 21-1 for the comparator modes. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY R/C-0 R/W-0 R/W-0 C1EVT C2EN C1EN C2OUTEN C1OUTEN ...
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... PIC24FJ128GA FAMILY NOTES: DS39747C-page 176 Preliminary © 2006 Microchip Technology Inc. ...
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... DD CVRSS = 0 CVREN CVRR V - REF © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected (CVR3:CVR0), with one range offering finer resolution. ...
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... Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits REF ) RSRC ) RSRC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = bit is set ‘0’ = bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 R/W-0 CVR2 CVR1 CVR0 bit bit is unknown © 2006 Microchip Technology Inc. ...
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... Configuration bits, whose actual locations are distributed among five locations in config- uration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY TABLE 23-1: FLASH CONFIGURATION WORDS LOCATIONS FOR ...
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... FWPSA WDTPS3 PO = Program-Once bit U = Unimplemented, read as ‘1’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-1 — — bit 16 U-1 R/PO-1 — ICS bit 8 R/PO-1 R/PO-1 R/PO-1 WDTPS2 WDTPS1 WDTPS0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Legend Readable bit -n = Value when unprogrammed © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY U-1 U-1 U-1 — — — R/PO-1 R/PO-1 R/PO-1 GCP ...
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... OSC PO = Program-Once bit ‘1’ = Bit is set Preliminary U-1 U-1 — — bit 16 R/PO-1 R/PO-1 FNOSC1 FNOSC0 bit 8 U-1 R/PO-1 R/PO-1 — POSCMD1 POSCMD0 bit Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. ...
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... FAMID0 bit 7 bit 23-14 Unimplemented: Read as ‘0’ bit 13-6 FAMID7:FAMID0: Device Family Identifier bits 00010000 = PIC24FJ128GA family bit 5-0 DEV5:DEV0: Individual Device Identifier bits 000101 = PIC24FJ64GA006 000110 = PIC24FJ96GA006 000111 = PIC24FJ128GA006 001000 = PIC24FJ64GA008 001001 = PIC24FJ96GA008 001010 = PIC24FJ128GA008 001011 = PIC24FJ64GA010 001100 = PIC24FJ96GA010 ...
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... DOT2:DOT0: Minor Revision Identifier bits Legend Readable bit DS39747C-page 184 — — — — — — — Reserved bit U = Unimplemented bit, read as ‘0’ Preliminary U U — — bit — — MAJRV2 bit DOT2 DOT1 DOT0 bit 0 © 2006 Microchip Technology Inc. ...
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... If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, V never exceed V by 0.3 volts. DD © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY FIGURE 23-1: Regulator Enabled (ENVREG tied EFC pins. When (10 μ ...
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... WDT option allows the user to enable the WDT for crit- ical code segments and disable the WDT during non-critical segments for maximum power savings. LPRC Control WDTPS3:WDTPS0 WDT Postscaler Counter 1:1 to 1:32.768 1 ms/4 ms Preliminary bit. When the FWDTEN Wake from Sleep WDT Overflow Reset © 2006 Microchip Technology Inc. ...
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... The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 23.6 In-Circuit Serial Programming PIC24FJ128GA family microcontrollers can be serially programmed while in the end application circuit ...
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... PIC24FJ128GA FAMILY NOTES: DS39747C-page 188 Preliminary © 2006 Microchip Technology Inc. ...
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... The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY The literal instructions that involve data movement may use some of the following operands: • ...
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... One of 16 source working registers ∈ {W0..W15} Wns WREG W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws Source W register ∈ Wso { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS39747C-page 190 Description Preliminary © 2006 Microchip Technology Inc. ...
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... Ws,#bit4 BSW BSW.C Ws,Wb BSW.Z Ws,Wb BTG BTG f,#bit4 BTG Ws,#bit4 BTSC BTSC f,#bit4 BTSC Ws,#bit4 © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Description WREG WREG = f + WREG Wd = lit10 + lit5 WREG + (C) WREG = f + WREG + ( lit10 + lit5 + ( .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND ...
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... WREG = f – – 2 Disable Interrupts for k Instruction Cycles Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Preliminary © 2006 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 None ...
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... NEG Ws,Wd NOP NOP NOPR POP POP f POP Wdo POP.D Wnd POP.S © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Description Find First One from Left (MSb) Side Find First One from Right (LSb) Side Go to Address Go to Indirect WREG = WREG = .IOR. WREG WREG = f ...
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... – – lit5 – WREG – (C) WREG = f – WREG – ( – lit10 – ( – Ws – ( – lit5 – ( WREG – f WREG = WREG – – lit5 – Wb Preliminary © 2006 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 None 1 1 None ...
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... XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY Description f = WREG – f – (C) WREG = WREG – f – ( – Wb – ( lit5 – Wb – ( Nibble Swap Byte Swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> ...
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... PIC24FJ128GA FAMILY NOTES: DS39747C-page 196 Preliminary © 2006 Microchip Technology Inc. ...
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... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. PIC24FJ128GA FAMILY 25.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an © 2006 Microchip Technology Inc. ...