PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet - Page 165

• Manufacturer Part Number: PIC24FJ64GA006-I/PT
• Description: 64 PIN, 64KB FLASH, 8 KB RAM, 53 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA006-I/PT

• A/d Inputs: 16 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 53
• Number Of Pins: 64
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 16 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 19-2:
19.3
19.3.1
To start serial shifting, a ‘1’ must be written to the
CRCGO bit.
The module incorporates a FIFO that is 8 deep when
PLEN (PLEN<3:0>) > 7, and 16 deep otherwise. The
data for which the CRC is to be calculated must first be
written into the FIFO. The smallest data element that
can be written into the FIFO is one byte. For example,
if PLEN = 5, then the size of the data is PLEN + 1 = 6.
The data must be written as follows:
Once data is written into the CRCWDAT MSb (as
defined
(VWORD<4:0>) increments by one. The serial shifter
starts shifting data into the CRC engine when
CRCGO = 1 and VWORD > 0. When the MSb is
shifted out, VWORD decrements by one. The serial
shifter continues shifting until the VWORD reaches 0.
Therefore, for a given value of PLEN, it will take
(PLEN + 1) * VWORD number of clock cycles to
complete the CRC calculations.
When VWORD reaches 8 (or 16), the CRCFUL bit will
be set. When VWORD reaches 0, the CRCMPT bit will
be set.
To continually feed data into the CRC engine, the rec-
ommended mode of operation is to initially “prime” the
FIFO with a sufficient number of words so no interrupt
is generated before the next word can be written. Once
that is done, start the CRC by setting the CRCGO bit to
‘1’. From that point onward, the VWORD bits should be
polled. If they read less than 8 or 16, another word can
be written into the FIFO.
© 2006 Microchip Technology Inc.
SDOx
XOR
User Interface
by
DATA INTERFACE
D
data[5:0] = crc_input[5:0]
p_clk
BIT 0
PLEN),
Q
data[7:6] = ‘bxx
CRC GENERATOR RECONFIGURED FOR x
the
D
BIT 4
p_clk
value
Q
of
VWORD
Preliminary
D
BIT 5
p_clk
PIC24FJ128GA FAMILY
Q
To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the
VWORD pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the con-
dition to generate an interrupt will not be met; therefore,
no interrupt will be generated (See Section 19.3.2
“Interrupt Operation”).
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
19.3.2
When VWORD4:VWORD0 makes a transition from a
value of ‘1’ to ‘0’, an interrupt will be generated.
19.4
19.4.1
If Sleep mode is entered while the module is operating,
the module will be suspended in its current state until
clock execution resumes.
19.4.2
To continue full module operation in Idle mode, the
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode; pending interrupt events will be
passed on, even though the module clocks are not
available.
Operation in Power Save Modes
16
INTERRUPT OPERATION
SLEEP MODE
IDLE MODE
+ x
12
CRC Read Bus
D
BIT 12
p_clk
+ x
Q
5
+ 1
DS39747C-page 163
CRC Write Bus
BIT 15
D
p_clk
Q