PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 206

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
18.2
In this mode, the USARTs use standard Non-Return-to-
Zero (NRZ) format (one Start bit, eight or nine data bits
and one Stop bit). The most common data format is
8 bits. An on-chip dedicated 8-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The Baud Rate Generator produces a
clock, either 16 or 64 times the bit shift rate, depending
on bit BRGH (TXSTAx<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTAx<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
18.2.1
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
Once the TXREGx register transfers the data to the
TSR register (occurs in one T
is empty and flag bit, TXx1IF (PIR1<4> for USART1,
FIGURE 18-1:
DS39609B-page 204
USART Asynchronous Mode
USART ASYNCHRONOUS
TRANSMITTER
TXIE
Interrupt
USART TRANSMIT BLOCK DIAGRAM
TXIF
TXEN
Baud Rate Generator
CY
SPBRG
), the TXREGx register
Baud Rate CLK
MSb
(8)
TX9D
TXREG Register
TSR Register
TX9
8
Data Bus
interrupt logic is tied to this bit, so the user has to poll this
PIR3<4> for USART2), is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXxIE
(PIE1<4> for USART1, PIE<4> for USART2). Flag bit
TXxIF will be set, regardless of the state of enable bit
TXxIE and cannot be cleared in software. It will reset
only when new data is loaded into the TXREGx register.
While flag bit TXIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. Status bit TRMT is a read-only
bit, which is set when the TSR register is empty. No
bit in order to determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
6.
7.
Note:
Note 1: The TSR register is not mapped in data
Initialize the SPBRGx register for the appropri-
ate baud rate. If a high-speed baud rate is
desired, set bit BRGH (Section 18.1 “USART
Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXxIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREGx register (starts
transmission).
LSb
2: Flag bit TXIF is set when enable bit TXEN
0
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
memory, so it is not available to the user.
is set.
TRMT
and Control
Pin Buffer
 2004 Microchip Technology Inc.
SPEN
TX pin