M25P64-VMF6P STMicroelectronics, M25P64-VMF6P Datasheet - Page 26

• Manufacturer Part Number: M25P64-VMF6P
• Description: 64 MBIT, LOW VOLTAGE, SERIAL FLASO 16 .30 LARGE JEDEC MS-013
• Manufacturer: STMicroelectronics

Specifications of M25P64-VMF6P

• Lead Free Status / Rohs Status: RoHS Compliant part

M25P64
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on V
correct value:
–
–
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write op-
erations during Power-up, a Power On Reset
(POR) circuit is included. The logic inside the de-
vice is held reset while V
On Reset (POR) threshold voltage, V
ations are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Sector Erase (SE),
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of t
elapsed after the moment that V
V
the device is not guaranteed if, by this time, V
still below V
Program or Erase instructions should be sent until
the later of:
Figure 20. Power-up Timing
26/38
WI
V
delay of t
V
threshold. However, the correct operation of
V CC (max)
V CC (min)
CC
SS
(min) at Power-up, and then for a further
at Power-down
V WI
V CC
CC
VSL
(min). No Write Status Register,
Reset State
Device
of the
Program, Erase and Write Commands are Rejected by the Device
CC
CC
Chip Selection Not Allowed
) until V
is less than the Power
CC
CC
rises above the
WI
reaches the
– all oper-
PUW
CC
has
is
tPUW
tVSL
–
–
These values are specified in
If the delay, t
above V
READ instructions even if the t
fully elapsed.
At Power-up, the device is in the following state:
–
–
Normal precautions must be taken for supply rail
decoupling, to stabilize the V
vice in a system should have the V
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when V
ing voltage, to below the Power On Reset (POR)
threshold voltage, V
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Read Access allowed
t
t
The device is in the Standby Power mode
The Write Enable Latch (WEL) bit is reset.
PUW
VSL
after V
CC
after V
(min), the device can be selected for
VSL
CC
CC
, has elapsed, after V
passed the V
passed the V
WI
, all operations are disabled
Device fully
accessible
CC
drops from the operat-
CC
Table
PUW
CC
time
WI
supply. Each de-
(min) level
delay is not yet
threshold
CC
8..
CC
AI04009C
rail decou-
has risen