M25P64-VMF6P STMicroelectronics, M25P64-VMF6P Datasheet
M25P64-VMF6P
Specifications of M25P64-VMF6P
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M25P64-VMF6P Summary of contents
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... February 2005 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 64 Mbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface Figure 1. Packages M25P64 PRELIMINARY DATA VDFPN8 (ME) 8x6mm (MLP8) SO16 (MF) 300 mils width ...
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... M25P64 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. VDFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. SO Connections SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial Data Output ( Serial Data Input ( Serial Clock ( Chip Select ( Hold (HOLD Write Protect ( SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Bus Master and Memory Devices on the SPI Bus Figure 6 ...
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... DC AND AC PARAMETERS Table 10. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 11. AC Measurement Conditions Figure 21.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 12. Capacitance Table 13. DC Characteristics Table 14. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 22.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 23.Write Protect Setup and Hold Timing during WRSR when SRWD Figure 24.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 M25P64 3/38 ...
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... M25P64 Figure 25.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 26.MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline . . . . . . . 34 Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 27.SO16 wide – 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . 35 Table 16. SO16 wide – ...
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... SUMMARY DESCRIPTION The M25P64 is a 64Mbit ( Serial Flash Memory, with advanced write protection mecha- nisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 128 sectors, each containing 256 pages ...
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... M25P64 SIGNAL DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives in- structions, addresses, and the data to be pro- grammed ...
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... Stand-by mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA= SPI Memory SPI Memory Device Device HOLD W M25P64 SPI Memory Device S HOLD W HOLD AI03746D MSB AI01438B 7/38 ...
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... M25P64 OPERATING FEATURES Page Programming To program one data byte, two instructions are re- quired: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which con- sists of four bytes plus data. This is followed by the internal Program cycle (of duration t To spread this overhead, the Page Program (PP) ...
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... The environments where non-volatile memory de- vices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P64 features the following data protection mechanisms: Power On Reset and an internal timer (t can provide protection against inadvertant changes while the power supply is outside the operating specification ...
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... M25P64 Hold Condition The Hold (HOLD) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S) Low ...
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... The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. High Voltage Generator I/O Shift Register 256 Byte Data Buffer 00000h 256 Bytes (Page Size) X Decoder M25P64 Status Register 7FFFFFh Size of the read-only memory area 000FFh AI08520 11/38 ...
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... M25P64 Table 3. Memory Organization Sector Address Range 127 7F0000h 126 7E0000h 125 7D0000h 124 7C0000h 123 7B0000h 122 7A0000h 121 790000h 120 780000h 119 770000h 118 760000h 117 750000h 116 740000h 115 730000h 114 720000h 113 710000h 112 700000h 111 6F0000h ...
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... M25P64 Address Range 140000h 14FFFFh 130000h 13FFFFh 120000h 12FFFFh 110000h 11FFFFh 100000h 10FFFFh 0F0000h 0FFFFFh 0E0000h 0EFFFFh 0D0000h 0DFFFFh 0C0000h 0CFFFFh 0B0000h 0BFFFFh ...
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... M25P64 INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C) ...
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... Instruction High Impedance – Power-up – Write Disable (WRDI) instruction completion (Figure 10.) – Write Status Register (WRSR) instruction completion – Page Program (PP) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion Instruction High Impedance M25P64 AI02281E AI03750D 15/38 ...
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... M25P64 Read Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, fol- lowed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (17h) ...
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... Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution Status Register Out MSB Table 2.) becomes protect- Status Register Out MSB AI02031E M25P64 17/38 ...
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... M25P64 Write Status Register (WRSR) The Write Status Register (WRSR) instruction al- lows new values to be written to the Status Regis- ter. Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex- ecuted. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL) ...
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... If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used Instruction Status Register High Impedance MSB AI02282D M25P64 19/38 ...
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... M25P64 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the mem- ...
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... High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) in- struction, while an Erase, Program or Write cycle Figure 15 progress, is rejected without having any ef- fects on the cycle that is in progress BIT ADDRESS DATA OUT MSB Read Data Bytes at Higher 47 DATA OUT MSB MSB M25P64 Speed AI04006 21/38 ...
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... M25P64 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex- ecuted. After the Write Enable (WREN) instruction has been decoded, the device sets the Write En- able Latch (WEL) ...
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... Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, Figure 17.. BP0) bits (see ed Instruction 24 Bit Address 23 22 MSB ) is initiated. While the Sector Erase cy- SE Table 2. and Table 3.) is not execut AI03751D M25P64 23/38 ...
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... M25P64 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex- ecuted. After the Write Enable (WREN) instruction has been decoded, the device sets the Write En- able Latch (WEL). ...
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... C Instruction D High Impedance Q Note: The value of the 8-bit Electronic Signature, for the M25P64, is 16h. The instruction sequence is shown in The Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S) High after the Electronic Signature has been read at least once. Sending additional clock cycles on Serial ...
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... M25P64 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied until V CC correct value: – V (min) at Power-up, and then for a further CC delay of t VSL – Power-down SS Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper Power-up and Power-down ...
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... Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains Threshold WI Parameter FFh). The Status Register contains 00h (all Status Register bits are 0). M25P64 Min. Max. Unit 30 µ ...
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... M25P64 MAXIMUM RATING Stressing the device outside the ratings listed in Table 9. may cause permanent damage to the de- vice. These are stress ratings only, and operation of the device at these, or any other conditions out- side those indicated in the Operating sections of Table 9. Absolute Maximum Ratings ...
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... Parameter Parameter Timing Reference Levels Test Condition OUT =25°C and a frequency of 20 MHz. A Min. Max. 2.7 3.6 –40 85 Min. Max 0. 0. Input and Output 0.7V CC 0.5V CC 0.3V CC AI07455 Min. Max M25P64 Unit V °C Unit Unit pF pF 29/38 ...
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... M25P64 Table 13. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Operating Current (READ) CC3 I Operating Current (PP) CC4 I Operating Current (WRSR) CC5 I Operating Current (SE) CC6 I Operating Current (BE) CC7 V Input Low Voltage IL V Input High Voltage ...
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... Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. Table 10. Parameter 3 (peak to peak) 3 (peak to peak) (max) C and Table 11. Min. Typ. Max. D. 0.1 0 100 100 160 M25P64 Unit MHz MHz ns ns V/ns V/ 31/38 ...
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... M25P64 Figure 22. Serial Input Timing S tCHSL C tDVCH D High Impedance Q Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL High Impedance Q 32/38 tSLCH tCHSH tCHDX tCLCH MSB IN tSHSL tSHCH tCHCL LSB IN AI01447C tSHWL AI07439 ...
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... Figure 24. Hold Timing HOLD Figure 25. Output Timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tHLCH tCHHL tCHHH tHLQZ tCH tCLQV tQLQH tQHQL M25P64 tHHCH tHHQX AI02032 tCL tSHQZ LSB OUT AI01449e 33/38 ...
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... M25P64 PACKAGE MECHANICAL Figure 26. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline Note: Drawing is not to scale. Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data Symbol Typ 0.40 D 8.00 D2 6.40 ddd E 6. ...
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... A1 L inches Typ Min 0.093 0.004 0.013 0.009 0.398 0.291 0.050 – 0.394 0.010 0.016 0° M25P64 C Max 0.104 0.012 0.020 0.013 0.413 0.299 – 0.419 0.030 0.050 8° 0.004 35/38 ...
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... Device tested with standard test flow Option blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating RoHS compliant For a list of available options (speed, package, etc.) or for further information on any aspect of this 36/38 M25P64 – device, please contact your nearest ST Sales Of- fice ...
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... Description of Revision revised BE (min (typ) and t (typ) changed. MLP8 package removed Table 14., AC Characteristics). SO16 Wide package specifications updated. modified in Figure 25., Output SHQZ INSTRUCTIONS M25P64 (Figure 19., Read Electronic Signature modified and tRES1 and tRES2 Timing. Figures moved below the section. 37/38 ...
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... M25P64 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...