DSPIC30F3011-30I/PT Microchip Technology Inc., DSPIC30F3011-30I/PT Datasheet - Page 60
DSPIC30F3011-30I/PT
Manufacturer Part Number
DSPIC30F3011-30I/PT
Description
16 BIT MCU/DSP 44LD 30MIPS 24 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F3011-30IPT.pdf
(244 pages)
Specifications of DSPIC30F3011-30I/PT
A/d Inputs
9-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
30
Interface
I2C/SPI/UART, USART
Ios
30
Memory Type
Flash
Number Of Bits
16
Package Type
44-pin TQFP
Programmable Memory
24K Bytes
Ram Size
1K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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dsPIC30F
6.4
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program 32
instructions at one time. RTSP may be used to program
multiple program memory panels, but the table pointer
must be changed at each panel boundary.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The instruction words loaded must always be from
an even group of 32 address boundary.
The basic sequence for RTSP programming is to set up
a table pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and 32 TBLWTH instructions are required to
load the 32 instructions.
All of the table write operations are single word writes
(2 instruction cycles), because only the table latches
are written. The actual programming operation is
started by a special sequence of writes to the NVM
control registers and takes nominally 2 msec.
The Flash Program Memory is readable, writable and
erasable during normal operation over the entire V
range.
6.5
The three SFRs used to read and write the program
Flash memory are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
6.5.1
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed, and
start of the programming cycle.
DS70082G-page 58
RTSP Operation
Control Registers
NVMCON REGISTER
Preliminary
DD
6.5.2
The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
6.5.3
The NVMADRU register is used to hold the upper byte
of the effective address. The NVMADRU register cap-
tures the EA<23:16> of the last table instruction that
has been executed.
6.5.4
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6 for
further details.
6.6
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the oper-
ation is finished. Setting the WR bit (NVMCON<15>)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
6.6.1
The user can erase one row of program Flash memory
at a time. The general process is:
1.
2.
3.
Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
Update the data image with the desired new
data.
Erase program Flash row.
a)
b)
c)
d)
e)
f)
g)
Programming Operations
Setup NVMCON register for multi-word,
program Flash, erase, and set WREN bit.
Write address of row to be erased into
NVMADRU/NVMDR.
Write ‘55’ to NVMKEY.
Write ‘AA’ to NVMKEY.
Set the WR bit. This will begin erase cycle.
CPU will stall for the duration of the erase
cycle.
The WR bit is cleared when erase cycle
ends.
NVMADR REGISTER
NVMADRU REGISTER
NVMKEY REGISTER
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
2004 Microchip Technology Inc.
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