CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 62

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

7. DESIGN CONSIDERATIONS
The CS8952 is a mixed-signal device containing
the high-speed digital and analog circuits required
to implement Fast Ethernet communication. It is
important the designer adhere to the following
guidelines and recommendations for proper and re-
liable operation of the CS8952. These guidelines
will also benefit the design with good EMC perfor-
mance.
7.1
The recommended connection of the twisted-pair
interface is shown if Figure 6. The unused cable
pairs are terminated to increase the common-mode
performance. Common-mode performance is also
improved by connecting the center taps of the RX
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
0
BIT
CS8952
Jabber Enable
Twisted Pair Interface
TX+
TX-
RX+
RX-
49.9 Ω
0.1 µF
80
81
91
92
NAME
Figure 6. Recommended Connection of Twisted-Pair Ports (Network Interface Card)
49.9 Ω
0.1 µF
Read/Write 1
TYPE
16
14
15
2
1
TG22-3506
RESET
T1
NC
3
0.01 µF
and TX input circuits to the DC-isolated ground
plane. The 0.01 µF capacitor C1 must provide 2 kV
(1,500 Vrms for 60 seconds) of isolation to meet
802.3 requirements. If a shielded RJ45 connector is
used (recommended), the shield should be connect-
ed to chassis ground.
7.2
Figure 7 shows the recommended connection for a
100BASE-FX interface to a Hewlett-Packard
HFBR-5103 fiber transceiver. Termination circuit-
ry may need to be revised for other fiber transceiv-
ers. The FX Drive bit in the Loopback, Bypass, and
Receiver Error Mask Register (address 18h) may
be used to tailor the PECL interface for 50 Ω or
150 Ω loads.
75 Ω
When set, the jabber function is enabled. When
clear, and if the CS8952 is in 10BASE-T full-duplex
or 10BASE-T ENDEC loopback mode, the jabber
function is disabled.
Note: When the National Compatibility Mode bit (bit
7) is set, the Jabber function may also be disabled
for 10BASE-T half-duplex, although this is not rec-
ommended.
2KV
10
12
11
6
5
7
100BASE-FX Interface
75 Ω
51 Ω
DESCRIPTION
51 Ω
51 Ω
51 Ω
51 Ω
51 Ω
1
2
3
4
5
6
7
8
CS8952
SHLD
SHLD
RJ-45
62