DP83256VF National Semiconductor, DP83256VF Datasheet - Page 91

• Manufacturer Part Number: DP83256VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor
• Series: PLAYER+™r

Specifications of DP83256VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83256VF

Symbol
E CE
R E W
E ACK
E INT
CBA5
CBA4
CBA3
CBA2
CBA1
CBA0
CBP
CBD7
CBD6
CBD5
CBD4
CBD3
CBD2
CBD1
CBD0
6 0 Signal Descriptions
CONTROL BUS INTERFACE
The Control Bus Interface consists of I O signals used to connect the PLAYER
The Control Bus is an asynchronous interface between the PLAYER
controller It provides access to 64 8-bit internal registers
In the PLAYER
Pin
73
72
75
74
83
82
81
80
77
76
96
95
94
93
92
91
90
89
86
a
I O
I O
I O
device the Control Bus address range has been expanded by 1-bit to 6 bits of address space
O
O
I
I
I
Control Enable An active-low TTL input signal which enables the Control Bus port for a read or write
cycle R E W CBA
Read E Write A TTL input signal which indicates a read Control Bus cycle(R E W
Control Bus cycle (R E W
or write cycle During a read cycle CBD
write cycle a microprocessor must hold CBD
it will remain low as long as E CE remains low ( E CE
occurred The Interrupt Condition Register (ICR) should be read in order to find out the source of the
interrupt Interrupts can be masked through the use of the Interrupt Condition Mask Register (ICMR)
Control Bus Address TTL input signals used to select the address of the register to be read or written
CBA5 is the most significant bit (MSB) and CBA0 is the least significant bit (LSB) of the address signals
Control Bus Parity A bidirectional TTL signal representing odd parity for the Control Bus data
(CBD
During a read cycle the signal is held valid by the PLAYER
During a write cycle the signal must be valid when E CE is low and must be held valid until E ACK
becomes low If incorrect parity is used during a write cycle the PLAYER
cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt Condition Register (ICR)
Control Bus Data Bidirectional TTL signals containing the data to be read from or written to a register
During a read cycle the signal is held valid by the PLAYER
During a write cycle the signal must be valid when E CE is low and must be held valid until E ACK
becomes low
E Acknowledge An active low TTL open drain output signal which indicates the completion of a read
E Interrupt An active low open drain TTL output signal indicating that an interrupt condition has
k
7 0
l
)
(Continued)
k
5 0
l
e
CBP and CBD
0)
91
k
7 0
k
7 0
l
a
k
Description
7 0
are valid as long as E ACK is low ( E ACK
device and a general purpose microprocessor or other
l
l
must be valid at the time E CE is low
valid until E ACK becomes low Once E ACK is low
e
0)
a
a
a
device to Station Management (SMT)
device as long as E ACK is low
device as long as E ACK is low
a
device will inhibit the write
e
1) or a write
e
0) During a