CY7C63823-PXC Cypress Semiconductor Corp, CY7C63823-PXC Datasheet - Page 57

• Manufacturer Part Number: CY7C63823-PXC
• Description: IC USB PERIPHERAL CTRLR 24-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63823-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
26.0
27.0
General Purpose I/O Interface
R
V
V
V
V
V
V
V
V
V
Clock
T
T
T
USB Driver
T
T
T
T
T
V
USB Data Timing
T
T
T
T
T
T
T
T
T
T
Notes:
Parameter
Parameter
6.
7.
ECLKDC
ECLK1
ECLK2
R1
R2
F1
F2
R
DRATE
DJR1
DJR2
DEOP
EOPR1
EOPR2
EOPT
UDJ1
UDJ2
LST
UP
ICR
ICF
HC
ILTTL
IHTTL
OL1
OL2
OL3
OH
CRS
Available only onCY7C639XX P2.7, P3.7, P0.0, P0.1; CY7C638XX P1.3,P1.4,P1.5,P1.6,P1.7.
Except for pins P1.0, P1.1 in GPIO mode.
DC Characteristics
AC Characteristics
External Clock Duty Cycle
External Clock Frequency
External Clock Frequency
Transition Rise Time
Transition Rise Time
Transition Fall Time
Transition Fall Time
Rise/Fall Time Matching
Output Signal Crossover Voltage
Low-speed Data Rate
Receiver Data Jitter Tolerance
Receiver Data Jitter Tolerance
Differential to EOP Transition Skew
EOP Width at Receiver
EOP Width at Receiver
Source EOP Width
Differential Driver Jitter
Differential Driver Jitter
Width of SE0 during Diff. Transition
Pull-up Resistance
Input Threshold Voltage Low, CMOS
mode
Input Threshold Voltage Low, CMOS
mode
Input Hysteresis Voltage, CMOS Mode High to low edge
Input Low Voltage, TTL Mode
Input HIGH Voltage, TTL Mode
Output Low Voltage, High Drive
Output Low Voltage, High Drive
Output Low Voltage, Low Drive
Output High Voltage
Description
Description
General
[7]
(continued)
[7]
[6]
[6]
Low to High edge
High to Low edge
I/O-pin Supply = 2.9-3.6V
I/O-pin Supply = 4.0-5.5V
I
I
I
I
External clock is the source of the
CPUCLK
External clock is not the source of the
CPUCLK
C
C
C
C
Ave. Bit Rate (1.5 Mbps ± 1.5%)
To next transition
To pair transition
Rejects as EOP
Accept as EOP
To next transition
To pair transition
OL1
OL1
OL2
OH
LOAD
LOAD
LOAD
LOAD
= 2 mA
= 50 mA
= 25 mA
= 8 mA
= 200 pF
= 600 pF
= 200 pF
= 600 pF
Conditions
Conditions
1.4775
V
0.187
Min.
40%
30%
Min.
1.25
–75
–45
–40
675
–95
–95
3%
2.0
0.5
CC
1.3
45
75
75
80
4
0
–
Typical
Typical
CY7C63310
CY7C638xx
CY7C639xx
1.5225
Max.
65%
55%
10%
Max.
0.8
0.8
0.4
0.4
300
300
125
100
330
210
12
2.0
1.5
Page 57 of 68
55
24
24
75
45
95
95
Mbps
Unit
V
V
V
MHz
MHz
Unit
KΩ
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
V
V
V
V
V
V
%
%
CC
CC
CC
V