CY7C63823-PXC Cypress Semiconductor Corp, CY7C63823-PXC Datasheet - Page 20

• Manufacturer Part Number: CY7C63823-PXC
• Description: IC USB PERIPHERAL CTRLR 24-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63823-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
10.1.5
Table 10-4. CPU/USB Clock Config CPUCLKCR) [0x30] [R/W]
Bit 7: Reserved
Bit 6: USB CLK/2 Disable
This bit only affects the USBCLK when the source is the external crystal oscillator. When the USBCLK source is the Internal
24-MHz Oscillator, the divide by two is always enabled
0 = USBCLK source is divided by two. This is the correct setting to use when the Internal 24-MHz Oscillator is used, or when
the external source is used with a 24-MHz clock
1 = USBCLK is undivided. Use this setting only with a 12-MHz external clock
Bit 5: USB CLK Select
This bit controls the clock source for the USB SIE
0 = Internal 24-MHz Oscillator. With the presence of USB traffic, the Internal 24-MHz Oscillator can be trimmed to meet the USB
requirement of 1.5% tolerance (see Table 10-6)
1 = External clock—external oscillator on CLKIN and CLKOUT if the external oscillator is enabled (the XOSC Enable bit set in
the CLKIOCR Register—Table 10-8), or the CLKIN input if the external oscillator is disabled. Internal Oscillator is not trimmed
to USB traffic. Proper USB SIE operation requires a 12-MHz or 24-MHz clock accurate to <1.5%.
Bit [4:1]: Reserved
Bit 0: CPU CLK Select
0 = Internal 24-MHz Oscillator.
1 = External crystal oscillator—External crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled,
CLKIN input if the external crystal oscillator is disabled
Note: the CPU speed selection is configured using the OSC_CR0 Register (Table 10-5)
Read/Write
Default
Field
Bit #
CPU/USB Clock Configuration
Reserved
7
–
0
USB CLK /2
Disable
R/W
6
0
USB CLK Select
R/W
5
0
4
–
0
3
–
0
Reserved
2
–
0
1
–
0
CY7C63310
CY7C638xx
CY7C639xx
Page 20 of 68
CPUCLK Select
R/W
0
0