CY7C63823-PXC Cypress Semiconductor Corp, CY7C63823-PXC Datasheet - Page 47

• Manufacturer Part Number: CY7C63823-PXC
• Description: IC USB PERIPHERAL CTRLR 24-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63823-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
19.0
19.1
Table 19-1. VREG Control Register (VREGCR) [0x73] [R/W]
20.0
The SIE allows the microcontroller to communicate with the
USB host at low-speed data rates (1.5 Mbps). The SIE
simplifies the interface between the microcontroller and USB
by incorporating hardware that handles the following USB bus
activity independently of the microcontroller:
Bit [7:2]: Reserved
Bit 1: Keep Alive
Keep Alive when set allows the voltage regulator to source up to 20µA of current when voltage regulator is disabled,
P12CR[0],P12CR[7] should be cleared.
0 = Disabled
1 = Enabled
Bit 0: VREG Enable
This bit turns on the 3.3V voltage regulator. The voltage regulator only functions within specifications when V
This block should not be enabled when V
0 = Disable the 3.3V voltage regulator output on the VREG/P1.2 pin
1 = Enable the 3.3V voltage regulator output on the VREG/P1.2 pin. GPIO functionality of P1.2 is disabled
Note: Use of the alternate drive on pins P1.3–P1.6 requires that the VREG Enable bit be set to enable the regulator and pro-
vide the alternate voltage
• Translate the encoded received data and format the data to
• CRC checking and generation. Flag the microcontroller if
• Address checking. Ignore the transactions not addressed
Read/Write
be transmitted on the bus.
errors exist during transmission.
to the device.
Default
Field
Bit #
VREG Control
USB Regulator Output
USB Serial Interface Engine (SIE)
7
–
0
6
–
0
CC
is below 4.35V—although no damage or irregularities will occur if it is enabled below 4.35V
5
–
0
Reserved
4
–
0
Firmware is required to handle the rest of the USB interface
with the following tasks:
• Send appropriate ACK/NAK/STALL handshakes.
• Token type identification (SETUP, IN, or OUT). Set the
• Place valid received data in the appropriate endpoint FIFOs.
• Send and update the data toggle bit (Data1/0).
• Bit stuffing/unstuffing.
• Coordinate enumeration by decoding USB device requests.
• Fill and empty the FIFOs.
• Suspend/Resume coordination.
• Verify and select Data toggle values.
appropriate token bit once a valid token is received.
3
–
0
2
–
0
Keep Alive
R/W
1
0
CY7C63310
CY7C638xx
CY7C639xx
CC
is above 4.35V.
Page 47 of 68
VREG Enable
R/W
0
0