CY7C63823-PXC Cypress Semiconductor Corp, CY7C63823-PXC Datasheet - Page 21

• Manufacturer Part Number: CY7C63823-PXC
• Description: IC USB PERIPHERAL CTRLR 24-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63823-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
10.1.6
Table 10-5. OSC Control 0 (OSC_CR0) [0x1E0] [R/W]
Bit [7:6]: Reserved
Bit 5: No Buzz
During sleep (the Sleep bit is set in the CPU_SCR Register—Table 11-1), the LVD and POR detection circuit is turned on
periodically to detect any POR and LVD events on the V
the duty cycle—Table 13-3). To facilitate the detection of POR and LVD events, the No Buzz bit is used to force the LVD and
POR detection circuit to be continuously enabled during sleep. This results in a faster response to an LVD or POR event during
sleep at the expense of a slightly higher than average sleep current
0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle
1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled
Note: The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below
Bit [4:3]: Sleep Timer [1:0]
Note: Sleep intervals are approximate
Bit [2:0]: CPU Speed [2:0]
The enCoRe II may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the
default CPU speed is one-eighth of the internal 24 MHz, or 3 MHz
Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24-MHz operating requirements
apply. An example of this scenario is a device that is configured to use an external clock, which is supplying a frequency of 20
MHz. If the CPU speed register’s value is 0b011, the CPU clock will be 20 MHz. Therefore the supply voltage requirements for
the device are the same as if the part was operating at 24 MHz. The operating voltage requirements are not relaxed until the
CPU speed is at 12 MHz or less
Important Note: Correct USB operations require the CPU clock speed to be at least eight times greater than the USB clock. If
the two clocks have the same source then the CPU clock divider should not be set to divide by more than 8. If the two clocks
have different sources, care must be taken to ensure that the maximum ratio of USB Clock/CPU Clock can never exceed 8
across the full specification range of both clock sources
Sleep Timer
Read/Write
CPU Speed
Default
Field
Bit #
[1:0]
00
01
10
11
[2:0]
000
001
010
011
100
101
110
111
OSC_CR0 Clock Configuration
Sleep Timer Clock
Frequency (Nominal)
512 Hz
64 Hz
8 Hz
1 Hz
CPU when Internal
Oscillator is selected
3 MHz (Default)
6 MHz
12 MHz
24 MHz
1.5 MHz
750 KHz
187 KHz
Reserved
7
–
0
Reserved
6
–
0
Sleep Period
(Nominal)
1.95 ms
15.6 ms
125 ms
1 sec
External Clock
Clock In / 8
Clock In / 4
Clock In / 2
Clock In / 1
Clock In / 16
Clock In / 32
Clock In / 128
Reserved
No Buzz
R/W
5
0
Watchdog Period
(Nominal)
6 ms
47 ms
375 ms
3 sec
CC
pin (the Sleep Duty Cycle bits in the ECO_TR are used to control
R/W
4
0
Sleep Timer [1:0]
R/W
3
0
R/W
2
0
CPU Speed [2:0]
R/W
1
0
CY7C63310
CY7C638xx
CY7C639xx
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R/W
0
0