STE10/100A STMicroelectronics, STE10/100A Datasheet - Page 32
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STE10/100A
Manufacturer Part Number
STE10/100A
Description
IC CTRLR PCI ETHERNET 128-PQFP
Manufacturer
STMicroelectronics
Datasheet
1.STE10100A.pdf
(82 pages)
Specifications of STE10/100A
Controller Type
Ethernet Controller, 10Base-T
Interface
PCI
Voltage - Supply
3.14 V ~ 3.46 V
Current - Supply
130mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-3663
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STE10/100A
Manufacturer:
ST
Quantity:
5 510
Company:
Part Number:
STE10/100A
Manufacturer:
STMicroelectronics
Quantity:
10 000
Registers and descriptors description
4.1.1
32/82
Table 6.
STE10/100A configuration registers description
CR0 (offset = 00h), LID - Loaded identification number of device and vendor
From EEPROM: Loaded from EEPROM
CR1 (offset = 04h), CSC - Configuration command and status
31~16
26, 25
22~21
15~0
Bit #
27
24
23
31
30
29
28
Configuration registers description
SDPR
Name
SDST
SFBB
LDID
SMA
LVID
SPE
SES
STA
---
---
Loaded device ID, the device ID number loaded from
serial EEPROM
Loaded vendor ID, the vendor ID number loaded
from serial EEPROM
Status parity error.
1: means that STE10/100A detected a parity error.
This bit will be set even if the parity error response
(bit 6 of CR1) is disabled.
Status system error.
1: means that STE10/100A asserted the system
error pin.
Status master abort.
1: means that STE10/100A received a master abort
and has terminated a master transaction.
Status target abort.
1: means that STE10/100A received a target abort
and has terminated a master transaction.
Reserved
Status device select timing. Indicates the timing of
the chip’s assertion of device select.
01: indicates a medium assertion of DEVSEL#.
Status data parity report.
1: when three conditions are met:
a. STE10/100A asserted parity error (PERR#) or it
detected parity error asserted by another device.
b. STE10/100A is operating as a bus master.
c. STE10/100A’s parity error response bit (bit 6 of
CR1) is enabled.
Status fast back-to-back.
Always 1, since STE10/100A has the ability to
accept fast back to back transactions.
Reserved
Description
EEPROM
EEPROM
Default
From
From
01
0
0
0
0
0
1
STE10/100A
RW type
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/O
R/O