ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 94

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 78:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
DcAddress register: bit allocation
DEVEN
R/W
7
0
13.1.2 DcAddress register (R/W: B7H/B6H)
13.1.3 DcMode register (R/W: B9H/B8H)
Table 77:
This command is used to set the USB assigned address in the DcAddress register
and enable the USB device. The DcAddress register bit allocation is shown in
Table
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the DcAddress register (accessible by the microcontroller) is not altered
by the bus reset. In response to the standard USB request, Set Address, the firmware
must issue a Write Device Address command, followed by sending an empty packet
to the host. The new device address is activated when the host acknowledges the
empty packet.
Code (Hex): B6/B7 — write/read DcAddress register
Transaction — write/read 1 word
Table 79:
This command is used to access the ISP1161A’s DcMode register, which consists of
1 byte (for bit allocation: see
The DcMode register controls the DMA bus width, resume and suspend modes,
interrupt activity and SoftConnect operation. It can be used to enable debug mode,
where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 — write/read Mode register
Transaction — write/read 1 word
Bit
7
6
5
4
3 to 0
Bit
7
6 to 0
R/W
6
0
78.
DcEndpointConfiguration register: bit description
DcAddress register: bit description
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
Symbol
DEVEN
DEVADR[6:0]
R/W
5
0
Rev. 03 — 23 December 2004
Description
Logic 1 indicates an enabled FIFO with allocated memory.
Logic 0 indicates a disabled FIFO (no bytes allocated).
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write).
Logic 1 indicates that this endpoint has double buffering.
Logic 1 indicates an isochronous endpoint. Logic 0 indicates a
bulk or interrupt endpoint.
Selects the FIFO size according to
Description
Logic 1 enables the device.
This field specifies the USB device address.
Full-speed USB single-chip host and device controller
R/W
4
0
Table
79). In 16-bit bus mode the upper byte is ignored.
DEVADR[6:0]
R/W
3
0
R/W
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 67
ISP1161A
R/W
1
0
R/W
93 of 134
0
0