ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 23

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
9397 750 13962
Product data
Fig 21. DC interrupt logic.
DcInterruptEnable register
DcInterrupt register
In isochronous mode, an interrupt is issued upon each packet transaction. The
firmware must take care of timing synchronization with the host. This can be done via
the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt
Enable register. If a Start-Of-Frame is lost, PSOF interrupts are generated every
1 ms. This allows the firmware to keep data transfer synchronized with the host. After
3 missed SOF events, the DC will enter ‘suspend’ state.
An alternative way of handling isochronous data transfer is to enable both the SOF
and the PSOF interrupts and disable the interrupt for each isochronous endpoint.
Interrupt control:
The behavior of this bit is given in
RESUME
IEP0OUT
SUSPND
EP0OUT
IERESM
IESUSP
RESET
IEP0IN
EP0IN
IERST
IESOF
IEEOT
Fig 22. Behavior of bit INTENA.
IEP14
EP14
SOF
EOT
. . .
. . .
Pin INT2: HIGH = de-assert; LOW = assert (individual interrupts are enabled).
. .
.
. .
.
MGT946
Rev. 03 — 23 December 2004
INT2 pin
occurs. For example,
Bit INTENA in the DcMode register is a global enable/disable bit.
an interrupt event
. .
.
. .
.
(during this time,
SOF asserted.)
INTENA = 0
DcMode register
Full-speed USB single-chip host and device controller
A
INTENA
Figure
SOF asserted
INTENA = 1
22.
LE
B
LATCH
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SOF asserted
INTENA = 0
INT2
C
004aaa198
ISP1161A
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