ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 86

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
12. DC DMA transfer
9397 750 13962
Product data
12.1 Selecting an endpoint for DMA transfer
Direct Memory Access (DMA) is a method to transfer data from one location to
another in a computer system, without intervention of the Central Processor Unit
(CPU). Many different implementations of DMA exist. The ISP1161A DC supports
two methods:
ISP1161A’s DC supports DMA transfer for all 14 configurable endpoints (see
Table
operation of ISP1161A’s DC can be interleaved with normal I/O mode access to other
endpoints.
The following features are supported:
The target endpoint for DMA access is selected via bits EPDIX[3:0] in the
DcDMAConfiguration register, as shown in
write) is automatically set by bit EPDIR in the associated ECR, to match the selected
endpoint type (OUT endpoint: read; IN endpoint: write).
Asserting input DACK2 automatically selects the endpoint specified in the
DcDMAConfiguration register, regardless of the current endpoint used for I/O mode
access.
Table 70:
•
•
•
•
•
•
8237 compatible mode: based on the DMA subsystem of the IBM personal
computers (PC, AT and all its successors and clones); this architecture uses the
Intel 8237 DMA controller and has separate address spaces for memory and I/O
DACK-only mode: based on the DMA implementation in some embedded RISC
processors, which has a single address space for both memory and I/O.
Single-cycle or burst transfers (up to 16 bytes per cycle)
Programmable transfer direction (read or write)
Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,
short/empty packet
Programmable signal levels on pins DREQ2 and EOT.
Endpoint
identifier
66). Only one endpoint at a time can be selected for DMA transfer. The DMA
1
2
3
4
5
6
7
8
9
Endpoint selection for DMA transfer
Rev. 03 — 23 December 2004
EPIDX[3:0]
0010
0011
0100
0101
0110
0111
1000
1001
1010
Full-speed USB single-chip host and device controller
Table
EPDIR = 0
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
70. The transfer direction (read or
Transfer direction
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A
EPDIR = 1
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
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