ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 126

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Product data
19.3 Typical software model
Remark: SH7709’s system clock input is for reference only. Please refer to SH7709’s
specification for its actual use.
ISP1161A can work under either 3.3 V or 5.0 V power supply; however, its internal
core actually works at 3.3 V. When using 3.3 V as the power supply input, the internal
DC/DC regulator will be bypassed. It is best to connect all four power supply pins
(V
Section
ISP1161A the flexibility to be used in an embedded system under either a 3.3 V or a
5 V power supply.
A typical SH7709 interface circuit is shown in
This section shows a typical software requirement for an embedded system that
incorporates ISP1161A. The software model for a digital still camera (DSC) is used
as the example for illustration (as shown in
software are required to make full use of the features in ISP1161A: the host stack and
the device stack. The device stack provides API directly to the application task for
device function; the host stack provides API for Class driver and device driver, both of
which provide API for application tasks for host function.
•
•
•
•
•
CC
RD and WR are common read and write signals. These signals are active LOW.
There are two DMA channel standard control lines:
DC). These signals have programmable active levels.
Two interrupt lines: INT1 (used by the host controller) and INT2 (used by the
device controller). Both have programmable level/edge and polarity (active HIGH
or LOW).
The internal 15 kΩ pull-down resistors are used for the HC’s two USB downstream
ports.
The RESET signal is active LOW.
(in each case one channel is used by the HC and the other channel is used by the
– DREQ1 and DACK1
– DREQ2 and DACK2
, V
reg(3.3)
14). All of the ISP1161A’s I/O pins are 5 V tolerant. This feature allows the
, V
hold1
Rev. 03 — 23 December 2004
and V
Full-speed USB single-chip host and device controller
hold2
) to the 3.3 V power supply (for more information see
Figure
Figure
63). Two components of system
62.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A
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