DS31412N Maxim Integrated Products, DS31412N Datasheet - Page 5

• Manufacturer Part Number: DS31412N
• Description: IC 12CH DS3/3 FRAMER 349-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31412N

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 960mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 349-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
LIST OF TABLES
Table 4-A. Applicable Telecommunications Standards ............................................................................ 8
Table 6-A. Register Map........................................................................................................................ 15
Table 6-B. Status Register Set Example................................................................................................ 17
Table 7-A. BERT/Loopback Interaction—Payload Bits .......................................................................... 20
Table 7-B. BERT/Loopback Interaction—Overhead Bits........................................................................ 21
Table 7-C. Common Line Interface Register Map.................................................................................. 22
Table 7-D. DS3/E3 Framer Register Map .............................................................................................. 33
Table 7-E. DS3 Alarm Criteria ............................................................................................................... 41
Table 7-F. E3 Alarm Criteria .................................................................................................................. 41
Table 7-G. BERT Register Map ............................................................................................................. 46
Table 7-H. HDLC Register Map ............................................................................................................. 55
Table 7-I. FEAC Register Map............................................................................................................... 64
Table 9-A. JTAG Instruction Codes ....................................................................................................... 72
Table 9-B. JTAG ID Code...................................................................................................................... 73
Table 10-A. Recommended DC Operating Conditions........................................................................... 74
Table 10-B. DC Electrical Characteristics .............................................................................................. 74
Table 11-A. Data Path Timing ............................................................................................................... 75
Table 11-B. TCCLK Data Path Timing................................................................................................... 75
Table 11-C. Line Loopback Timing ........................................................................................................ 77
Table 11-D. Microprocessor Interface Timing ........................................................................................ 78
Table 11-E. JTAG Interface Timing ....................................................................................................... 83
Table 12-A. Global Pin Assignments (Sorted by Signal Name).............................................................. 84
Table 12-B. Per-Framer Pin Assignments (Sorted by Signal Name)...................................................... 84
Table 13-A. Thermal Properties, Natural Convection............................................................................. 89
Table 13-B. Theta-JA (q
) vs. Airflow.................................................................................................... 89
JA
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