DS21FF42 Maxim Integrated Products, DS21FF42 Datasheet - Page 14

• Manufacturer Part Number: DS21FF42
• Description: IC FRAMER T1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3. DS21FT42 (4 X 3) PCB LAND PATTERN Figure 4-1
The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same
pattern that would be seen as viewed through the MCM from the top.
W
M
C
D
G
H
N
R
U
A
B
E
F
K
L
P
T
V
Y
J
rsync
rsync
tneg
tneg
sync
rpos
rpos
rpos
tpos
rser
tclk
tser
tsig
rclk
rser
tclk
tser
rclk
1
rch
blk
rch
blk
ts
1
1
1
1
2
2
2
2
2
2
5
5
5
5
5
6
6
6
6
6
dvdd
dvdd
tsync
rsync
rneg
sync
rneg
tpos
tpos
rneg
tneg
rpos
rclk
rsig
rsig
tsig
rch
sys
tclk
sys
2
blk
clk
clk
ts
1
1
1
1
2
2
2
2
2
8
5
5
5
2
5
6
6
6
6
6
sync1
rsync
tsync
dvdd
tpos
tneg
rneg
tpos
dvss
rneg
rsig
tser
rser
rclk
tsig
rclk
tser
sys
tclk
rch
blk
3
clk
ts
1
1
1
1
3
2
2
8
2
5
5
5
8
8
8
2
6
8
6
tsync
tsync
rsync
dvdd
dvss
sync
sync
dvss
rpos
rpos
cs2*
tser
tsig
rsig
tsig
sys
rser
sys
rsig
rser
4
clk
clk
ts
ts
4
1
1
3
1
2
3
3
8
2
5
5
8
8
8
9
3
6
6
tsync
tsync
rsync
tsync
dvss
tneg
sync
tneg
tpos
tser
rpos
tclk
sys
tclk
sys
tclk
rsig
rch
tsig
sys
5
clk
clk
blk
clk
4
1
3
1
3
3
ts
3
2
3
8
5
8
8
8
8
7
7
7
6
7
rsync
dvss
clksi
rser
rsig
rclk
tser
rch
blk
tclk
rch
blk
6
1
3
3
3
7
7
7
7
7
rsync
mclk
dvdd
tsync
dvdd
rneg
tpos
sync
tser
rser
7
ts
4
8
1
4
3
7
2
7
7
7
rser4
rsig4
sync
dvss
tneg
sync
cs1*
rch
sys
rch
8
blk
clk
blk
10
4
4
ts
4
2
7
ts
9
rneg
rpos
rneg
dvss
rneg
tser
rclk
rclk
tsig
sys
9
10
clk
10
4
4
4
3
1
9
9
7
10
tneg
tpos
rpos
tpos
tsig
rclk
rsig
tsig
rclk
jtdi
10
10
10
14 of 114
4
4
4
3
9
9
11
rsync
rpos
rneg
rser
rsig
nc
nc
nc
nc
nc
10
10
10
9
9
12
dvdd
tneg
rser
sys
rch
clk
11
10
blk
10
10
nc
nc
nc
nc
nc
3
13
rsync
tsync
tsync
test
tclk
tclk
nc
nc
nc
nc
10
10
10
9
9
14
tpos
tneg
jtclk
fs1
fs0
ns
nc
nc
nc
nc
9
9
15
rsync
sync
cs3*
tsig
bts
ns
nc
ns
nc
nc
11
ts
9
9
16
dvdd
tsync
tsync
jtms
dvss
tser
rser
rser
tser
int*
tclk
wr*
nc
nc
nc
nc
nc
nc
nc
nc
12
12
12
11
11
11
3
9
3
17
jtrst*
mux
jtdot
rneg
sync
rclk
sys
D6
D7
rch
blk
rch
blk
nc
nc
nc
nc
nc
nc
A6
A7
nc
12
clk
12
12
11
11
11
ts
18
rsync
tpos
tneg
tsig
tclk
tsig
rclk
rd*
A4
A5
D4
D5
nc
nc
nc
nc
nc
nc
nc
nc
12
12
11
11
11
11
11
tssyn
19
rpos
tneg
dvdd
rpos
rsig
A2
A3
D2
D3
12
12
12
11
11
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
3
c
20
rneg
tpos
dvss
rsig
tser
D0
D1
nc
nc
nc
nc
nc
nc
A0
A1
nc
nc
nc
nc
nc
12
12
12
12
3