DS3112 Maxim Integrated Products, DS3112 Datasheet - Page 56

• Manufacturer Part Number: DS3112
• Description: IC MUX TEMPE T3/E3 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3112

• Controller Type: Framer, Multiplexer
• Interface: Parallel/Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5-1. T3 Alarm Criteria
Note 1: RAI can also be indicated via FEAC codes in the C-Bit Parity Mode
Note 2: LOS is not defined for unipolar (binary) operation.
CONDITION
Idle Signal
ALARM/
(Note 1)
LOS
LOF
RAI
AIS
Alarm Indication Signal
Properly framed 1010...
pattern, which is aligned
with the 1 just after each
overhead bit and all C bits
are set to zero
Loss Of Signal
(Note 2)
Loss Of Frame
Too many F bits or M bits in
error
Remote Alarm Indication
(This is also referred to as
SEF/AIS in Bellcore GR-
820)
Inactive: X1 = X2 = 1
Active: X1 = X2 = 0
Properly framed 1100...
pattern, which is aligned
with the 11 just after each
overhead bit and the C bits
in Subframe 3 are zero.
DEFINITION
In each 84-bit information
field, the properly aligned
10... pattern is detected with
less than 4-bit errors (out of
84 possible) for 1024
consecutive information bit
fields (1.95ms) and all C bits
are majority decoded to be
zero during this time
192 consecutive zeros
Three or more F bits in error
out of 16 consecutive, or 2 or
more M bits in error out of
four consecutive
X1 and X2 = 0 for four
consecutive M frames (426µs)
In each 84-bit information
field, the properly aligned
1100... pattern is detected with
less than 4-bit errors (out of
84 possible) for 1024
consecutive information bit
fields (1.95ms) and the C bits
in Subframe 3 are majority
decoded to be zero during this
time.
56 of 133
SET CRITERIA
In each 84 bit information
field, the properly aligned
10... pattern is detected with
4 or more bit errors (out of 84
possible) for 1024
consecutive information bit
fields (1.95ms)
No EXZ events over a 192-
bit window that starts with
the first one received
Synchronization occurs
X1 and X2 = 1 for four
consecutive M frames
(426µs)
In each 84-bit information
field, the properly aligned
1100... pattern is detected
with four or more bit errors
(out of 84 possible) for 1024
consecutive information bit
fields (1.95ms)
CLEAR CRITERIA
DS3112