DS2482S-800+T&R Maxim Integrated Products, DS2482S-800+T&R Datasheet - Page 8

• Manufacturer Part Number: DS2482S-800+T&R
• Description: IC MASTER I2C-1WIRE 8CH 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS2482S-800+T&R

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 3.3 V, 5V
• Current - Supply: 750µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1-Wire Speed (1WS)
The 1WS bit determines the timing of any 1-Wire communication generated by the DS2482. All 1-Wire slave
devices support standard speed (1WS = 0), where the transfer of a single bit (t
65µs. Many 1-Wire device can also communicate at a higher data rate, called Overdrive speed. To change from
standard to Overdrive speed, a 1-Wire device needs to receive an Overdrive Skip ROM or Overdrive Match ROM
command, as explained in the device data sheets. The change in speed occurs immediately after the 1-Wire device
has received the speed-changing command code. The DS2482 must take part in this speed change to stay
synchronized. This is accomplished by writing to the Configuration Register with the 1WS bit being 1 immediately
after the 1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the Configuration Register
with the 1WS bit being 0 followed by a 1-Wire Reset command changes the DS2482 and any 1-Wire devices on
the active 1-Wire line back to standard speed.
Status Register
The read-only Status Register is the general means for the DS2482 to report bit-type data from the 1-Wire side, 1-
Wire busy status and its own reset status to the host processor. All 1-Wire communication commands and the
Device Reset command position the read pointer at the Status Register for the host processor to read with minimal
protocol overhead. Status information is updated during the execution of certain commands only. Details are given
in the description of the various status bits below.
Status Register Bit Assignment
1-Wire Busy (1WB)
The 1WB bit reports to the host processor whether the 1-Wire line is busy. During 1-Wire communication 1WB is 1;
once the command is completed, 1WB returns to its default 0. Details on when 1WB changes state and for how
long it remains at 1 are found in the Function Commands section.
Presence Pulse Detect (PPD)
The PPD bit is updated with every 1-Wire Reset command. If the DS2482 detects a presence pulse from a 1-Wire
device at t
there is no presence pulse or if the 1-Wire line is shorted during a subsequent 1-Wire Reset command.
Short Detected (SD)
The SD bit is updated with every 1-Wire Reset command. If the DS2482 detects a logic 0 on the 1-Wire line at t
during the Presence Detect cycle, the SD bit will be set to 1. This bit will return to its default 0 with a subsequent 1-
Wire Reset command provided that the short has been removed. If SD is 1, PPD will be 0. The DS2482 cannot
distinguish between a short and a DS1994 or DS2404 signaling a 1-Wire interrupt. For this reason, if a
DS2404/DS1994 is used in the application, the interrupt function must be disabled. The interrupt signaling is
explained in the respective device data sheets.
Logic Level (LL)
The LL bit reports the logic state of the active 1-Wire line without initiating any 1-Wire communication. The 1-Wire
line is sampled for this purpose every time the Status Register is read. The sampling and updating of the LL bit
takes place when the host processor has addressed the DS2482 in read mode (during the acknowledge cycle),
provided that the Read Pointer is positioned at the Status Register.
Device Reset (RST)
If the RST bit is 1, the DS2482 has performed an internal reset cycle, either caused by a power-on reset or from
executing the Device Reset command. The RST bit is cleared automatically when the DS2482 executes a Write
Configuration command to restore the selection of the desired 1-Wire features.
bit 7
DIR
MSP
bit 6
TSB
during the Presence Detect cycle, the PPD bit will be set to 1. This bit will return to its default 0 if
SBR
bit 5
RST
bit 4
bit 3
LL
bit 2
SD
PPD
bit 1
8 of 23
1WB
bit 0
SLOT
in Figure 3) is completed within
SI