DS2482S-800+T&R Maxim Integrated Products, DS2482S-800+T&R Datasheet - Page 13

• Manufacturer Part Number: DS2482S-800+T&R
• Description: IC MASTER I2C-1WIRE 8CH 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS2482S-800+T&R

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 3.3 V, 5V
• Current - Supply: 750µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5. Write-0 Time Slot
Figure 6. Write-1 and Read-Data Time Slot
NOTE on Figure 7: Depending on its internal state, a 1-Wire slave device will transmit data to its master (e.g., the
DS2482). When responding with a 0, a 1-Wire slave will start pulling the line low during t
generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, a 1-
Wire slave will not hold the line low at all, and the voltage starts rising as soon as t
sheets use the term t
specifications and cannot be distinguished from each other.
1-Wire Write Byte
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
V
V
V
V
V
V
0V
0V
IH1
IH1
IL1
IL1
cc
cc
t
t
RL
F1
F1
instead of t
Pullup (see Fig. 2)
Pullup (see Fig. 2)
t
W1L
W1L
A5h
Data Byte
Writes single data byte to selected 1-Wire IO channel.
To write commands or data to a 1-Wire IO channel; equivalent to
executing eight 1-Wire Single Bit commands, but faster due to less I²C
traffic.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code and data byte will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
8 × t
bit) of the data byte.
Begins maximum 262.5ns after falling SCL edge of the LS bit of the data
byte (i.e., before the data byte acknowledge).
NOTE: The bit order on the I²C bus and the 1-Wire line is different.
(1-Wire: LS-bit first; I²C: MS-bit first) Therefore, 1-Wire activity cannot
begin before the DS2482 has received the full data byte.
Status Register (for busy polling)
1WB (set to 1 for 8 × t
1WS, SPU, APU apply
to describe a read-data time slot. Technically, t
t
t
SLOT
MSR
MSR
+ maximum 262.5ns, counted from falling edge of the last bit (LS
13 of 23
t
W0L
DS2482 Pulldown
DS2482 Pulldown
t
SLOT
SLOT
t
SLOT
)
t
REC0
1-W Slave Pulldown
W1L
is over. 1-Wire device data
RL
and t
W1L
; its internal timing
W1L
have identical